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data sheet the information contained in this document is being issued in advance of the production cycle for the device. the parameters for the device may change before final production or nec corporation, at its own discretion, may withdraw the device prior to its production. mos integrated circuit m pd789415, 789416, 789417 8-bit single-chip microcontroller preliminary product information document no. u12302ej1v0pm00 (1st edition) date published june 1997 j printed in japan 1997 the m pd789415, m pd789416, and m pd789417 are m pd789417 sub-series products (lcd drivers) of the 78k/0s series. these microcontrollers feature an 8-bit cpu, lcd controller/driver, i/o ports, timers, a serial interface, a/d converters, a comparator, and interrupt control circuits. the instruction set of the m pd789415, m pd789416, and m pd789417 is a subset of the 78k/0 series standard instruction set. in addition, a flash memory product ( m pd78f9418) that can operate within the same voltage range as the mask rom models, and a range of related development tools are being developed. the functions of these microcontrollers are described in the following users manual. refer to this manual when designing a system based on any of these microcontrollers. m pd789407 and m pd789417 sub-series users manual: under development features ? rom and ram sizes item data memory product name internal high-speed ram lcd data ram package m pd789415 12 kbytes 512 8 bits 28 8 bits m pd789416 16 kbytes m pd789417 24 kbytes ? variable instruction execution time: from high-speed (0.4 m s with the main system clock running at 5.0 mhz) to ultra-low speed (122 m s with the subsystem clock running at 32.768 khz) ? 43 i/o ports ? serial interface channel: switchable between three-wire serial i/o and uart modes ? lcd controller/driver: ? up to 28 segment signal outputs ? up to 4 common signal outputs ? bias switchable between 1/2 and 1/3 ? seven a/d converters with an 10-bit resolution ? six timers: ? 16-bit timer/counter ? two 8-bit timer/event counters ? 8-bit timer/counter ? clock timer ? watchdog timer ? power supply voltage v dd : 1.8 to 5.5 v 80-pin plastic qfp (14 14 mm) 80-pin plastic tqfp (fine pitch) (12 12 mm) program memory (rom)
2 m pd789415, 789416, 789417 applications aps compact cameras, manometers, and rice cookers ordering information part number package m pd789415gc- -8bt 80-pin plastic qfp (14 14 mm) m pd789415gk- -be9 80-pin plastic tqfp (fine pitch) (12 12 mm) m pd789416gc- -8bt 80-pin plastic qfp (14 14 mm) m pd789416gk- -be9 80-pin plastic tqfp (fine pitch) (12 12 mm) m pd789417gc- -8bt 80-pin plastic qfp (14 14 mm) m pd789417gk- -be9 80-pin plastic tqfp (fine pitch) (12 12 mm) remark indicates the rom code number.
3 m pd789415, 789416, 789417 78k/0s series development the 78k/0s series products are shown below. the sub-series names are indicated in frames. under development 42/44-pin for small-scale, general- purpose applications 28-pin 78k/0s series 80-pin 80-pin 42/44-pin 42-pin pd789026 m m m m device developed by adding a 16-bit timer to the pd789014 with built-in uart bus and capable of low-voltage (1.8 v) operation pd789014 m for lcd driving pd789417 m device developed by enhancing the a/d function of the pd789407 device developed by adding an a/d function and enhancing the timers of the pd789026 pd789407 m for assp pd789800 m device for a pc keyboard, with a built-in usb function device for a pc monitor, with a built-in usb function and synchronizing separator pd789806y m the y sub-series products are compatible with the i 2 c bus. the following table lists the major differences in functions between the sub-series. function timer 8-bit 10-bit 8-bit serial minimum sub-series 8-bit 16-bit clock wdt a/d a/d d/a interface v dd value m pd789026 4 k-16 k 1 ch 1 ch - 1 ch -- - 1 ch (uart: 1 ch) 34 pins 1.8 v m pd789014 2 k-4 k 2 ch - 22 pins lcd driving m pd789417 12 k-24 k 3 ch 1 ch 1 ch 1 ch - 7 ch - 1 ch (uart: 1 ch) 43 pins 1.8 v m pd789407 12 k-24 k 7 ch - assp m pd789800 8 k 2 ch -- 1 ch -- - 2 ch (usb: 1 ch) 31 pins 4.0 v m pd789806y 16 k 2 ch -- 1 ch -- - 2 ch (usb: 1 ch, i 2 c: 1 ch) 20 pins 4.5 v small-scale general purpose rom size i/o
4 m pd789415, 789416, 789417 78k/0 series development the 78k/0 series products are shown below. the sub-series names are indicated in frames. pd78044f 80-pin basic sub-series for fip driving, with a total of 34 display outputs pd78083 pd78002 pd78002y pd780001 pd78014 pd78014y pd78018f pd78018fy pd78014h pd780024 pd780024y pd780034 pd780034y 64-pin 64-pin device developed by enhancing the a/d function of the pd780024 low emi noise version of the pd78018f 64-pin low emi noise version of the pd78018f, developed by enhancing its serial i/o bus pd78054 pd78054y pd78058f pd78058fy pd780058 pd780058y note 42/44-pin 64-pin 64-pin 64-pin 64-pin 80-pin 80-pin low emi noise version of the pd78054 device developed by adding uart and d/a functions to the pd78014 and enhancing the i/o bus low-voltage (1.8 v) version of the pd78014, with enhanced rom and ram variations device developed by adding a/d and 16-bit timer functions to the pd78002 device developed by adding a/d functions to the pd78002 basic series for control use with built-in uart bus and capable of low-voltage (1.8 v) operation in production under development the y sub-series products are compatible with the i 2 c bus. pd78044h pd780228 pd780208 80-pin 100-pin 100-pin device developed by enhancing the i/o and fip c/d functions of the pd78044f, with a total of 53 display outputs device developed by enhancing the i/o and fip c/d functions of the pd78044h, with a total of 48 display outputs device developed by adding n-channel, open-drain input/output ports, with a total of 34 display outputs for driving fip tm pd780924 pd780964 64-pin 64-pin device developed by enhancing the a/d function of the pd780924 built-in inverter control circuit and uart bus. low emi noise version. for inverter control 80-pin 80-pin pd78064 pd78064b pd780308 100-pin 100-pin 100-pin device developed by enhancing the sio bus of the pd78064, with expanded rom and ram low emi noise version of the pd78064 basic sub-series for lcd driving, with built-in uart for lcd driving pd780308y pd78064y pd78098b device developed by adding the iebus controller to the pd78054 low emi noise version of the pd78098 device supporting iebus tm 80-pin low emi noise version of the pd78054, developed by enhancing its serial i/o bus pd780018 note pd780018y 100-pin device developed by enhancing the serial i/o bus of the pd78078 and limiting its functions 78k/0 series pd78070ay 100-pin 100-pin device with enhanced external interface, developed by adding a timer to the pd78054 rom-less version of the pd78078 100-pin low emi noise version of the pd78078 used for control m m m m m pd78070a m m m m m m m m m m m m m m m m m m m m m m m m m m pd78098 m m m m m m m m m m m m m m m m m m m m m m m 100-pin 80-pin pd780973 device developed by modifying the automobile meter controller/driver of the pd780805 to a general-purpose version device with built-in automobile meter controller/driver for meter control pd780805 m m 64-pin pd78p0914 device with pwm output, lv digital code decoder, and hsync counter for lv m m m m pd78078 m pd78075b m pd78078y m pd78075by m note device in the planning stage
5 m pd789415, 789416, 789417 the following table lists the major functional differences between the sub-series. function timer 8-bit 10-bit 8-bit serial minimum external sub-series 8-bit 16-bit clock wdt a/d a/d d/a interface v dd value expansion m pd78075b 32 k-40 k 4 ch 1 ch 1 ch 1 ch 8 ch - 2 ch 3 ch 88 pins 1.8 v m pd78078 48 k-60 k (uart: 1 ch) m pd78070a - 61 pins 2.7 v m pd780018 48 k-60 k - 2 ch (3-wire time-division: 1 ch) 88 pins m pd780058 24 k-60 k 2 ch 2 ch 3 ch (uart time-division: 1 ch) 68 pins 1.8 v m pd78058f 48 k-60 k 3 ch 69 pins 2.7 v m pd78054 16 k-60 k (uart: 1 ch) 2.0 v m pd780034 8 k-32 k - 8 ch - 3 ch (uart : 1 ch, 3-wire time division: 1 ch) 51 pins 1.8 v m pd780024 8 ch - m pd78014h 2 ch 53 pins m pd78018f 8 k-60 k m pd78014 8 k-32 k 2.7 v m pd780001 8 k -- 1 ch 39 pins - m pd78002 8 k-16 k 1 ch - 53 pins m pd78083 - 8 ch 1 ch (uart: 1 ch) 33 pins 1.8 v - m pd780964 8 k-32 k 3 ch note - 1 ch - 8 ch - 2 ch 47 pins 2.7 v m pd780924 8 ch - (uart: 2 ch) for fip m pd780208 32 k-60 k 2 ch 1 ch 1 ch 1 ch 8 ch -- 2 ch 74 pins 2.7 v - driving m pd780228 48 k-60 k 3 ch -- 1 ch 72 pins 4.5 v m pd78044h 32 k-48 k 2 ch 1 ch 1 ch 68 pins 2.7 v m pd78044f 16 k-40 k 2 ch for lcd driving m pd780308 48 k-60 k 2 ch 1 ch 1 ch 1 ch 8 ch -- 3 ch (uart time division: 1 ch) 57 pins 2.0 v - m pd78064b 32 k 2 ch m pd78064 16 k-32 k (uart: 1 ch) m pd78098b 40 k-60 k 2 ch 1 ch 1 ch 1 ch 8 ch - 2 ch 3 ch 69 pins 2.7 v m pd78098 32 k-60 k (uart: 1 ch) m pd780973 24 k-32 k 3 ch 1 ch 1 ch 1ch 5 ch -- 2 ch 56 pins 4.5 v - m pd780805 40 k-60 k 2 ch 8 ch (uart: 1 ch) 39 pins 2.7 v for lv m pd78p0914 32 k 6 ch -- 1 ch 8 ch -- 2 ch 54 pins 4.5 v note one 10-bit timer rom size i/o for control use for inverter control for support- ing the iebus for meter control
6 m pd789415, 789416, 789417 functions item m pd789415 m pd789416 m pd789417 built-in memory rom 12 kbytes 16 kbytes 24 kbytes high-speed ram 512 bytes lcd data ram 28 bytes instruction cycle built-in function for changing the instruction execution time 0.4/1.6 m s (operation with main system clock running at 5.0 mhz) 122 m s (operation with subsystem clock running at 32.768 khz). general-purpose registers 8 bits 8 registers instruction set ? 16-bit operations ? bit manipulations (such as set, reset, and test) i/o ports total of 43 port pins ? 7 cmos input pins ? 32 cmos input/output pins ? 4 n-channel open-drain pins (dielectric strength of 12 v) a/d converters seven channels with 10-bit resolution comparator with timer output control function serial interface ? switchable between three-wire serial i/o and uart modes lcd controller/driver ? up to 28 segment signal outputs ? up to 4 common signal outputs ? bias switchable between 1/2 and 1/3 timers ? 16-bit timer/counter ? 8-bit timer/counter ? two 8-bit timer/event counters ? clock timer ? watchdog timer timer output two outputs vector interrupt maskable 12 internal and 4 external interrupts sources non-maskable internal interrupt power supply voltage v dd = 1.8 to 5.5 v operating ambient temperature t a = - 40 to + 85 c package ? 80-pin plastic qfp (14 14 mm) ? 80-pin plastic tqfp (fine pitch) (12 12 mm)
7 m pd789415, 789416, 789417 contents 1. pin configuration (top view) ............................................................................................ 9 2. block diagram ............................................................................................................... ........ 11 3. pin functions ................................................................................................................ .......... 12 3.1 port pins .................................................................................................................. ......................... 12 3.2 non-port pins ............................................................................................................................... ..... 13 3.3 pin input/output circuits and handling of unused pins................................................................. 14 4. cpu architecture ............................................................................................................ ..... 17 4.1 memory space ............................................................................................................................... ... 17 4.2 data memory addressing ................................................................................................................. 18 4.3 processor registers ......................................................................................................................... 19 5. peripheral hardware functions.................................................................................. 23 5.1 ports ............................................................................................................................... ................... 23 5.2 clock generator............................................................................................................. ................... 30 5.3 16-bit timer/counter ........................................................................................................ ................ 35 5.4 8-bit timer/event counter................................................................................................... ............. 40 5.5 clock timer................................................................................................................. ...................... 47 5.6 watchdog timer.............................................................................................................. .................. 50 5.7 10-bit a/d converter....................................................................................................... .................. 54 5.8 comparator ............................................................................................................................... ........ 59 5.9 serial interface channel 0 .................................................................................................. .............. 62 5.10 lcd controller/driver ....................................................................................................................... 73 6. interrupt functions.......................................................................................................... .. 79 6.1 interrupt function types .................................................................................................................. 79 6.2 interrupt sources and configuration ............................................................................................... 79 6.3 interrupt function control registers........................................................................................ ....... 82 7. standby function ............................................................................................................ .... 89 7.1 standby function .............................................................................................................................. 8 9 7.2 standby function control register ................................................................................................. 92 8. reset functions .............................................................................................................. ...... 93 9. mask options ................................................................................................................ .......... 95 10. instruction set overview.................................................................................................. 96 10.1 legend ............................................................................................................................... ............... 96 10.2 operations ............................................................................................................................... ......... 98 11. electrical characteristics (target values).......................................................... 103
8 m pd789415, 789416, 789417 12. package dimensions......................................................................................................... ... 117 appendix a development tools.............................................................................................. 119 appendix b related documents ............................................................................................ 121
9 m pd789415, 789416, 789417 1. pin configuration (top view) ? 80-pin plastic qfp (14 14 mm) ? 80-pin plastic tqfp (fine pitch)(12 12 mm) m pd789415gc- -8bt m pd789415gk- -be9 m pd789416gc- -8bt m pd789416gk- -be9 m pd789417gc- -8bt m pd789417gk- -be9 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 v dd1 bias v lc0 v lc1 v lc2 v ss1 com0 com1 com2 com3 s0 s1 s2 s3 s4 s5 s6 s7 s8 s9 p50 p51 p52 p53 p20/sck/asck p21/so/txd p22/si/rxd p23/cmptout0/to2 p24/intp0/ti0 p25/intp1/ti1 p26/intp2/to5 p27/intp3/cpt5 av ss p60/ani0/cmpin0 p61/ani1/cmpref0 p62/ani2 p63/ani3 p64/ani4 p65/ani5 p66/ani6 s10 s11 s12 s13 s14 s15 p93/s16 p92/s17 p91/s18 p90/s19 p87/s20 p86/s21 p85/s22 p84/s23 p83/s24 p82/s25 p81/s26 p80/s27 av dd av ref p40/kr0 p41/kr1 p42/kr2 p43/kr3 p44/kr4 p45/kr5 ic xt1 xt2 v dd0 v ss0 x1 x2 reset p46 p47 p00 p01 p02 p03 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 cautions 1. connect the ic pin (internally connected) directly to v ss0 or v ss1 . 2. connect the av dd pin to v dd0 . 3. connect the av ss pin to v ss0 .
10 m pd789415, 789416, 789417 ani0-ani6 : analog input p60-p66 : port 6 asck : asynchronous serial input p80-p87 : port 8 av dd : analog power supply p90-p93 : port 9 av ref : analog reference voltage reset : reset av ss : analog ground rxd : receive data bias : lcd power supply bias control s0-s27 : segment output cmpin0 : comparator input sck : serial clock cmpref0 : comparator reference si : serial input cmptout0 : comparator output so : serial output com0-com3: common output ti0, ti1 : timer input cpt5 : capture trigger input to2, to5 : timer output ic : internally connected txd : transmit data intp0-intp3 : interrupt from peripherals v dd0 , v dd1 : power supply kr0-kr5 : key return v lc0 -v lc2 : lcd power supply p00-p03 : port 0 v ss0 , v ss1 : ground p20-p27 : port 2 x1, x2 : crystal (main system clock) p40-p47 : port 4 xt1, xt2 : crystal (subsystem clock) p50-p53 : port 5
11 m pd789415, 789416, 789417 2. block diagram 78k/0s cpu core rom ram v dd0 v dd1 v ss0 v ss1 ic ti0/intp0/p24 8-bit timer event/counter 0 p00-p03 port0 p20-p27 port2 p40-p47 port4 p50-p53 port5 p60-p66 port6 p80-p87 port8 p90-p93 port9 system control ti1/intp1/p25 8-bit timer event/counter 1 to2/cmptout0 /p23 8-bit timer counter 2 to5/intp2/p26 cpt5/intp3/p27 16-bit timer counter 5 watch timer watchdog timer serial interface sck/asck/p20 si/rxd/p22 so/txd/p21 comparator cmptout0/to2/p23 cmpref0/ani1/p61 cmpin0/ani0/p60 a/d converter ani0/cmpin0/p60 ani2/p62- ani6/p66 ani1/cmpref0/p61 av dd av ss av ref v lc0 -v lc2 bias s0-s15 s15/p93-s19/p90 s20/p87-s27/p80 com0-com3 lcd controller/ driver reset x1 x2 xt1 xt2 interrupt control intp0/ti0/p24 intp1/ti1/p25 intp2/to5/p26 intp3/cpt5/p27 kr0/p40-kr5/p45 remark the size of the built-in rom varies depending on the model.
12 m pd789415, 789416, 789417 3. pin functions 3.1 port pins pin name i/o function when reset also used as p00-p03 i/o port 0 4-bit input/output port can be set to either input or output in 1-bit units when used as an input port, whether the built-in pull-up resistor is to be used can be specified by software. input - p20 i/o input sck/asck p21 so/txd p22 si/rxd p23 cmptout0/to2 p24 intp0/ti0 p25 intp1/ti1 p26 intp2/to5 p27 intp3/cpt5 p40-p45 i/o input kr0-kr5 p46, p47 - p50-p53 i/o port 5 4-bit n-channel open-drain input/output port can be set to either input or output in 1-bit units whether a pull-up resistor is to be incorporated can be specified by a mask option. input - p60 input port 6 input ani0/cmpin0 p61 7-bit input-only port ani1/cmpref0 p62-p66 ani2-ani6 p80-p87 i/o port 8 8-bit input/output port can be set to either input or output in 1-bit units when used as an input port, whether the built-in pull-up resistor is to be used can be specified by software. input s27-s20 p90-p93 i/o port 9 4-bit input/output port can be set to either input or output in 1-bit units when used as an input port, whether the built-in pull-up resistor is to be used can be specified by software. input s19-s16 port 2 8-bit input/output port can be set to either input or output in 1-bit units when used as an input port, whether the built-in pull-up resistor is to be used can be specified by software. port 4 8-bit input/output port can be set to either input or output in 1-bit units when used as an input port, whether the built-in pull-up resistor is to be used can be specified by software.
13 m pd789415, 789416, 789417 3.2 non-port pins pin name i/o function when reset also used as intp0 input input p24/ti0 intp1 p25/ti1 intp2 p26/to5 intp3 p27/cpt5 kr0-kr5 input key return signal detection input p40-p45 si input serial data input to serial interface input p22/rxd so output serial data output from serial interface input p21/txd sck i/o serial clock input/output for serial interface input p20/asck asck input serial clock input to asynchronous serial interface input p20/sck rxd input serial data input to asynchronous serial interface input p22/si txd output serial data output from asynchronous serial interface input p21/so ti0 input external count clock input to 8-bit timer (tm0) input p24/intp0 ti1 input external count clock input to 8-bit timer (tm1) input p25/intp1 to2 output 8-bit timer (tm2) output input p23/cmptout0 to5 output 16-bit timer (tm5) output input p26/intp2 cpt5 input capture edge input input p27/intp3 cmptout0 output comparator output input p23/to2 cmpin0 input comparator input input p60/ani0 cmpref0 input comparator reference voltage input input p61/ani1 ani0 input a/d converter analog input input p60/cmpin0 ani1 p61/cmpref0 ani2-ani6 p62-p66 av ref - a/d converter reference voltage -- av ss - a/d converter ground potential -- av dd - a/d converter analog power supply -- s0-s15 output lcd controller/driver segment signal output output - s16-s19 input p93-p90 s20-s27 p87-p80 com0-com3 output lcd controller/driver common signal output output - v lc0 -v lc2 - lcd driving voltage -- bias - supply voltage for lcd driving -- x1 input connected to crystal for main system clock oscillation -- x2 - -- xt1 input connected to crystal for subsystem clock oscillation -- xt2 - -- reset input system reset input input - v dd0 - positive supply voltage for ports -- v dd1 - positive supply voltage for circuits other than ports -- v ss0 - port section ground potential -- v ss1 - ground potential of circuits other than ports -- ic - internally connected directly to v ss0 or v ss1 -- external interrupt input for which effective edges (rising and/or falling edges) can be specified
14 m pd789415, 789416, 789417 3.3 pin input/output circuits and handling of unused pins table 3-1 lists the types of input/output circuits for each pin and explains how unused pins are handled. figure 3-1 shows the configuration of each type of input/output circuit. table 3-1. type of input/output circuit for each pin and handling of unused pins pin name i/o circuit type i/o recommended connection of unused pins p00-p03 5-h i/o separately connected to v dd0 , v dd1 , v ss0 , or v ss1 via respective resistors p20/sck/asck 8-c p21/so/txd p22/si/rxd p23/cmptout0/to2 10-b p24/intp0/ti0 8-c p25/intp1/ti1 p26/intp2/to5 p27/intp3/cpt5 p40/kr0-p45/kr5 p46, p47 5-h p50-p53 13-q p60/ani0/cmpin0 9-d input p61/ani1/cmpref0 p62/ani2-p66/ani6 9-c p80/s27-p87/s20 17-f i/o p90/s19-p93/s16 s0-s15 17-b output open com0-com3 18-a v lc0 -v lc2 -- bias open (alternatively, connected to v ss0 or v ss1 via a resistor independently of the other pins, when none of v lc0 to v lc2 are used, however) xt1 input connected to v ss0 or v ss1 , via a resistor, independently of the other pins xt2 - open reset 2 input - ic -- connected directly to v ss0 or v ss1
15 m pd789415, 789416, 789417 figure 3-1. pin input/output circuits (1/2) schmitt trigger input with hysteresis type 2 in type 5-h pull-up enable data output disable input enable v dd0 p-ch v dd0 p-ch in/out n-ch type 10-b v ss0 pull-up enable data open drain output disable v dd0 p-ch v dd0 p-ch in/out n-ch v ss0 v ss0 type 8-c pull-up enable data output disable v dd0 p-ch v dd0 p-ch in/out n-ch v ss0 type 9-c type 9-d in comparator + e + e v ref (threshold voltage) av ss p-ch n-ch input enable type 13-q output data output disable in/out v dd0 n-ch buffer with medium dielectric strength input enable type 17-b p-ch v lc0 v lc1 n-ch p-ch n-ch v lc2 v ss1 seg data p-ch out n-ch pull-up resistor (mask option) p-ch n-ch in input enable comparator v ref av ss (threshold voltage)
16 m pd789415, 789416, 789417 figure 3-1. pin input/output circuits (2/2) type 17-f p-ch v lc0 v lc1 v lc2 v ss1 seg data p-ch n-ch n-ch data output disable p-ch v dd0 v ss0 n-ch seg output disable input enable p-ch v dd0 pull-up enable type 18-a com data out p-ch v lc0 v lc1 n-ch v lc2 v ss1 p-ch n-ch p-ch n-ch n-ch p-ch in/out
17 m pd789415, 789416, 789417 4. cpu architecture 4.1 memory space the m pd789415, m pd789416, and m pd789417 can each access up to 64 kbytes of memory space. figure 4-1 shows the memory map. figure 4-1. memory map special function register 256 8 bits built-in high-speed ram 256 8 bits ram space for lcd data 28 8 bits program memory space data memory space program area program area callt table area unusable vector table area built-in rom note unusable ffffh ffffh feffh fd00h fcffh nnnnh 0080h 007fh 0040h 003fh 0024h 0023h 0000h fa1ch fa1bh 0000h fa00h f9ffh nnnnh nnnnh+1 note the size of the built-in rom varies depending on the model. (see the following table.) product name last address of built-in rom nnnnh m pd789415 2fffh m pd789416 3fffh m pd789417 5fffh
18 m pd789415, 789416, 789417 4.2 data memory addressing each of the m pd789415, m pd789416, and m pd789417 is provided with a wide range of addressing modes to make memory manipulation as efficient as possible. a data memory area (fd00h to ffffh) can be accessed using a unique addressing mode according to its use, such as a special function register (sfr). figure 4-2 illustrates the data memory addressing modes. figure 4-2. data memory addressing modes special function register (sfr) 256 8 bits built-in high-speed ram 512 8 bits ram space for lcd data 28 8 bits built-in rom note direct addressing register indirect addressing based addressing sfr addressing short direct addressing unusable unusable ffffh ff20h ff1fh ff00h feffh fe20h fe1fh fd00h fcffh fa1ch fa1bh fa00h f9ffh nnnnh 0000h nnnnh+1 note the size of built-in rom varies depending on the model. (see the following table.) product name last address of built-in rom nnnnh m pd789415 2fffh m pd789416 3fffh m pd789417 5fffh
19 m pd789415, 789416, 789417 4.3 processor registers 4.3.1 controller registers (1) program counter (pc) the pc is a 16-bit register for holding address information that indicates the next program to be executed. figure 4-3. program counter configuration 15 pc 0 (2) program status word (psw) the psw is an 8-bit register for holding the status of the cpu according to the results of instruction execution. figure 4-4. program status word configuration 7 ie 0 z 0 ac 0 0 1 cy psw (a) interrupt enable flag (ie) ie is used to control whether interrupt requests are to be accepted by the cpu. (b) zero flag (z) z is set (1) if the result of operation is zero. otherwise, it is reset (0). (c) auxiliary carry flag (ac) ac is set (1) if the result of the operation has a carry from bit 3 or a borrow to bit 3. otherwise, it is reset (0). (d) carry flag (cy) cy is used to indicate whether an overflow or underflow has occurred during the execution of a subtract or add instruction. (3) stack pointer (sp) sp is a 16-bit register for holding the start address of a stack area. the stack area can be specified only in an area (fd00h to feffh) of built-in high-speed ram. figure 4-5. stack pointer configuration 15 sp 0 caution a reset input makes the sp content undefined. before executing an instruction, always initialize the sp.
20 m pd789415, 789416, 789417 4.3.2 general-purpose registers each device has eight 8-bit general-purpose registers (x, a, c, b, e, d, l, and h). these registers can be used as 16-bit registers (two 8-bit registers used in pairs like ax, bc, de, and hl) as well as ordinary 8-bit registers. these registers are identified using functional register names (x, a, c, b, e, d, l, h, ax, bc, de, and hl) and absolute register names (r0 to r7 and rp0 to rp3). figure 4-6. general register configuration (a) absolute register names r7 r6 r5 r4 r3 r2 r1 r0 8-bit processing 16-bit processing rp3 rp2 rp1 rp0 15 0 7 0 (b) functional register names h l d e b c a x 8-bit processing 16-bit processing hl de bc ax 15 0 7 0
21 m pd789415, 789416, 789417 4.3.3 special function registers (sfrs) the sfrs are used as peripheral hardware mode registers and control registers. they are mapped in a 256-byte space, from ff00h to ffffh. table 4-1. special function registers (1/2) number of bits manipulated simultaneously 1 bit 8 bits 16 bits ff00h port 0 p0 r/w - 00h ff02h port 2 p2 - ff04h port 4 p4 - ff05h port 5 p5 - ff06h port 6 p6 r - ff08h port 8 p8 r/w - ff09h port 9 p9 - ff10h transmission shift register txs sio0 w - - ffh reception buffer register rxb r - - undefined ff14h 10-bit a/d conversion result register adcr r/w -- ff15h ff16h 16-bit compare register 5 cr50l cr50 w -- ffffh ff17h cr50h ff18h 16-bit timer register 5 tm5 r -- 0000h ff19h ff1ah 16-bit capture register 5 tcp5 -- undefined ff1bh ff20h port mode register 0 pm0 r/w - ffh ff22h port mode register 2 pm2 - ff24h port mode register 4 pm4 - ff25h port mode register 5 pm5 - ff28h port mode register 8 pm8 - ff29h port mode register 9 pm9 - ff42h timer clock selection register 2 tcl2 - - 00h ff48h 16-bit timer mode control register 5 tmc5 - ff4ah clock timer mode control register wtm - ff4eh comparator mode register 0 cmprm0 - ff50h 8-bit compare register 0 cr00 w - - undefined ff51h 8-bit timer register 0 tm0 r - - 00h ff53h 8-bit timer mode control register 0 tmc0 r/w - ff54h 8-bit compare register 1 cr10 w - - undefined ff55h 8-bit timer register 1 tm1 r - - 00h notes 1. when read with an 8-bit memory manipulation instruction, the eight high-order bits of the 10-bit conversion result are read. 2. cr50, tm5, and tcp5 are designed for 16-bit access. they can also be accessed in 8-bit mode, however. in 8-bit access mode, use direct addressing. 3. 16-bit access is allowed only with short direct addressing. when reset r/w symbol special function register (sfr) name address note 1 note 3 note 3 note 2 note 2 note 3 note 3 note 2
22 m pd789415, 789416, 789417 table 4-1. special function registers (2/2) number of bits manipulated simultaneously 1 bit 8 bits 16 bits ff57h 8-bit timer mode control register 1 tmc1 r/w - 00h ff58h 8-bit compare register 2 cr20 w - - undefined ff59h 8-bit timer register 2 tm2 r - - 00h ff5bh 8-bit timer mode control register 2 tmc2 r/w - ff70h asynchronous serial interface mode register asim - ff71h asynchronous serial interface status register asis r - - ff72h serial operation mode register 0 csim0 r/w - ff73h baud rate generator control register brgc - - ff80h a/d converter mode register adm - ff84h a/d input selection register ads - ffb0h lcd display mode register lcdm - ffb1h lcd port selector lps - ffb2h lcd clock control register lcdc - ffe0h interrupt request flag register 0 if0 - ffe1h interrupt request flag register 1 if1 - ffe4h interrupt mask flag register 0 mk0 - ffh ffe5h interrupt mask flag register 1 mk1 - ffech external interrupt mode register 0 intm0 - - 00h ffedh external interrupt mode register 1 intm1 - - fff0h subsystem clock oscillation mode register sckm - fff2h subclock control register css - fff3h pull-up resistor option register 1 pu1 - fff4h pull-up resistor option register 2 pu2 - fff5h key return mode register krm - fff7h pull-up resistor option register 0 pu0 - fff9h watchdog timer mode register wdtm - fffah oscillation settling time selection register osts - - 04h fffbh processor clock control register pcc - 02h when reset r/w symbol special function register (sfr) name address
23 m pd789415, 789416, 789417 5. peripheral hardware functions 5.1 ports 5.1.1 port functions the m pd789415, m pd789416, and m pd789417 are provided with the ports shown in figure 5-1. these ports are used to enable several types of control. table 5-1 lists the functions of each port. these ports, while originally designed as digital input/output ports, can also be used for other functions, as summarized in chapter 3 . figure 5-1. port types p50 p53 p00 p03 p60 p66 p80 p87 p40 p47 p90 p93 port 5 port 6 ? ? ? ? ? ? port 9 ? ? ? ? ? ? ? ? ? ? port 8 ? ? ? ? ? ? ? ? ? port 4 ? ? ? ? ? ? ? ? ? p20 p27 port 2 port 0 ? ? ? ? ? ? ? ? ?
24 m pd789415, 789416, 789417 table 5-1. port functions port name pin name description port 0 p00-p03 input/output port. each bit of the port can be separately specified as being for input or output. a port used for input can be connected to an internal pull-up resistor by means of software specification. port 2 p20-p27 input/output port. each bit of the port can be separately specified as being for input or output. a port used for input can be connected to an internal pull-up resistor by means of software specification. port 4 p40-p47 input/output port. each bit of the port can be separately specified as being for input or output. a port used for input can be connected to an internal pull-up resistor by means of software specification. port 5 p50-p53 n-channel open-drain input/output port. each bit of the port can be separately specified as being for input or output. whether the port itself is to contain a pull-up resistor is specified with a mask option. port 6 p60-p66 input-only port port 8 p80-p87 input/output port. each bit of the port can be separately specified as being for input or output. a port used for input can be connected to an internal pull-up resistor by means of software specification. port 9 p90-p93 input/output port. each bit of the port can be separately specified as being for input or output. a port used for input can be connected to an internal pull-up resistor by means of software specification.
25 m pd789415, 789416, 789417 5.1.2 port configuration the hardware configuration of the ports is as follows. table 5-2. port configuration item configuration control register port mode register (pmm, where m = 0, 2, 4, 5, 8, or 9) pull-up resistor option register (pu0 to pu2) port pins total: 43 (36 input/output and 7 input-only pins) pull-up resistors total: 36 (internal pull-up resistors can be used as specified by software, and whether a port itself is to contain pull-up resistors can be specified with a mask option) figure 5-2. basic port configuration internal bus wr pu rd wr port wr pm note output latch (pmn) pmmn v dd p-ch pmn note each bit of the pull-up resistor option registers (pu0 to pu2) pu00 and pu04 for pu0 pu120 to pu127 for pu1 pu280, pu282, pu284, pu286, pu290, and pu292 for pu2 for details, see (2) in section 5.1.3 . caution figure 5-2 shows the basic configuration of the input/output ports. the configuration differs depending on the functions assigned to the dual-function pins. remark pmmn : bit n of port mode register m, where m = 0, 2, 4, 5, 8, or 9, and n = 0 to 7 pmn : bit n of port m rd : port read signal wr : port write signal
26 m pd789415, 789416, 789417 5.1.3 port function control registers the following two types of registers are used to control the ports. ? port mode registers (pm0, pm2, pm4, pm5, pm8, and pm9) ? pull-up resistor option registers (pu0 to pu2) (1) port mode registers (pm0, pm2, pm4, pm5, pm8, and pm9) the port mode registers separately specify each port bit as being for input or output. each port mode register is manipulated using a 1-bit or 8-bit memory manipulation instruction. a reset input writes ffh into the port mode registers. when port pins are used for secondary functions, the corresponding port mode register and output latch must be set or reset as described in table 5-3. caution when port 2 is acting as an output port, and its output level is changed, an interrupt request flag is set, because this port is also used as the input for an external interrupt. to use port 2 in output mode, therefore, the interrupt mask flag must be set to 1 in advance.
27 m pd789415, 789416, 789417 table 5-3. port mode register and output latch settings for using secondary functions secondary function name input/output p23 cmptout0 output 0 0 to2 output 0 0 p24 intp0 input 1 ti0 input 1 p25 intp1 input 1 ti1 input 1 p26 intp2 input 1 to5 output 0 0 p27 intp3 input 1 cpt5 input 1 p40-p45 note kr0-kr5 input 1 p60 ani0 input 1 cmpin0 input 1 p61 ani1 input 1 cmpref0 input 1 p62-p66 ani2-ani6 input 1 p80-p87 s27-s20 output 0 0 p90-p93 s19-s16 output 0 0 note to use the secondary functions, set the key return mode register (krm) to 1. (see (6) in section 6.3 .) caution when port 2 is being used as a serial interface, it is necessary to specify whether the port is an input or output port, and to set the output latch accordingly. see table 5-13 for an explanation of how to make this specification. remark : dont care pm : port mode register p : port output latch p pm pin name
28 m pd789415, 789416, 789417 figure 5-3. port mode register format 1 pm27 pm47 1 pm87 1 1 pm26 pm46 1 pm86 1 1 pm25 pm45 1 pm85 1 1 pm24 pm44 1 pm84 1 pm03 pm23 pm43 pm53 pm83 pm93 pm02 pm22 pm42 pm52 pm82 pm92 pm01 pm21 pm41 pm51 pm81 pm91 pm00 pm20 pm40 pm50 pm80 pm90 pm0 pm2 pm4 pm5 pm8 pm9 76543210 symbol address when reset r/w ff20h ff22h ff24h ff25h ff28h ff29h ffh ffh ffh ffh ffh ffh r/w r/w r/w r/w r/w r/w pmmn 0 1 pmn pin input/output mode selection (m = 0, 2, 4, 5, 8, or 9; n = 0 to 7) output mode (output buffer on) input mode (output buffer off) (2) pull-up resistor option registers (pu0 to pu2) these registers are used to specify whether an internal pull-up resistor is to be used at each port. an internal pull-up resistor can be used only for a port that is in input mode and for which the use of the internal pull-up resistor is selected using the corresponding pull-up resistor option register. if a port is in output mode, an internal pull-up resistor is not used with it, even if the use of an internal pull-up resistor has been specified using the corresponding option register. the same applies when the port pin is used for a secondary function. pu0 to pu2 are manipulated using a 1-bit or 8-bit memory manipulation instruction. a reset input clears pu0 to pu2 to 00h.
29 m pd789415, 789416, 789417 figure 5-4. format of pull-up resistor option register 0 pm internal pull-up resistor selection note (m = 0 or 4) 0 0 0 pu04 0 0 0 pu00 pu0 address when reset r/w fff7h 00h r/w 76543210 pu0m 0 1 internal pull-up resistor not used internal pull-up resistor used note pu0 selects whether internal pull-up resistors are to be used in 8-bit units, except for port 0, for which internal pull-up resistors can be used with only four bits (p00 to p03). caution bits 1, 2, 3, 5, 6, and 7 must be fixed to 0. figure 5-5. format of pull-up resistor option register 1 p2 internal pull-up resistor selection note pu127 pu126 pu125 pu124 pu123 pu122 pu121 pu120 pu1 address when reset r/w fff3h 00h r/w 76543210 pu12m 0 1 internal pull-up resistor not used internal pull-up resistor used note pu1 selects whether internal pull-up resistors are to be used in 1-bit units. figure 5-6. format of pull-up resistor option register 2 pm internal pull-up resistor selection note (m = 8 or 9; n = 0, 2, 4, or 6) 00 pu292 pu290 pu286 pu284 pu282 pu280 pu2 address when reset r/w fff4h 00h r/w 76543210 pu2mn 0 1 internal pull-up resistor not used internal pull-up resistor used note pu2 selects whether internal pull-up resistors are to be used in 2-bit units (bit n and bit n+1). caution bits 6 and 7 must be fixed to 0.
30 m pd789415, 789416, 789417 5.2 clock generator 5.2.1 clock generator functions the clock generator generates the clock pulse to be supplied to the cpu and peripheral hardware. there are two types of system clock oscillators: ? main system clock oscillator this circuit generates a frequency of 1 to 5.0 mhz. oscillation can be stopped by executing the stop instruction or by using the processor clock control register. ? subsystem clock oscillator this circuit generates 32.768 khz. oscillation can be stopped by using the suboscillation mode register. 5.2.2 clock generator configuration the clock generator consists of the following hardware. table 5-4. clock generator configuration item configuration control register processor clock control register (pcc) suboscillation mode register (sckm) subclock control register (css) oscillators main system clock oscillator subsystem clock oscillator
31 m pd789415, 789416, 789417 figure 5-7. clock generator block diagram subsystem clock oscillation mainsystem clock oscillation standby controller wait controller f xt x1 x2 xt1 xt2 f x f x 2 2 f xt 2 1/2 prescaler prescaler 8-bit timer 2 clock timer lcd clock clock for peripheral hardware cpu clock (f cpu ) selector stop mcc pcc1 cls css0 internal bus suboscillation mode register frc scc internal bus subclock control register processor clock control register
32 m pd789415, 789416, 789417 5.2.3 clock generator control registers the clock generator is controlled using the following registers. ? processor clock control register (pcc) ? suboscillation mode register (sckm) ? subclock control register (css) (1) processor clock control register (pcc) the pcc selects a cpu clock and specifies a corresponding frequency division ratio. it is manipulated using a 1-bit or 8-bit memory manipulation instruction. a reset input loads 02h into the pcc. figure 5-8. processor clock control register format control of main system clock oscillator operation mcc00000 pcc1 0 pcc symbol address when reset r/w fffbh 02h r/w 76543210 mcc 0 1 operation enabled operation disabled cpu clock (f cpu ) selection note css0 0 0 1 1 f x f x /2 2 f xt /2 pcc1 0 1 0 1 (0.2 s) (0.8 s) (61 s) m m m note a cpu clock is selected by a combination of the pcc1 flag in the processor clock control register (pcc) and the css0 flag in the subclock control register (css). (see (3) in section 5.2.3 .) caution bit 0 and bits 2 to 6 must be fixed to 0. remarks 1. f x : main system clock oscillation frequency 2. f xt : subsystem clock oscillation frequency 3. the parenthesized values apply to operation with f x = 5.0 mhz or f xt = 32.768 khz. 4. minimum instruction execution time: 2 f cpu ?f cpu = 0.2 m s : 0.4 m s ?f cpu = 0.8 m s : 1.6 m s ?f cpu = 61 m s : 122 m s
33 m pd789415, 789416, 789417 (2) suboscillation mode register (sckm) the sckm selects a feedback resistor for the subsystem clock, and controls the oscillation of the clock. the subsystem clock is manipulated using a 1-bit or 8-bit memory manipulation instruction. a reset input clears the sckm to 00h. figure 5-9. suboscillation mode register format feedback resistor selection 000000frcscc sckm symbol address when reset r/w fff0h 00h r/w 76543210 frc 0 1 internal feedback resistor used internal feedback resistor not used control of subsystem clock oscillator operation scc 0 1 operation enabled operation disabled caution bits 2 to 7 must be fixed to 0.
34 m pd789415, 789416, 789417 (3) subclock control register (css) the css specifies whether the main system or subsystem clock osc illator is to be selected. it also specifies how the cpu clock operates. it is manipulated using a 1-bit or 8-bit memory manipulation instruction. a reset input clears the css to 00h. figure 5-10. subclock control register format cpu clock operation status 0 0 cls css0 0000 css address when reset r/w fff2h 00h r/w 76543210 cls 0 1 operation based on the output of the divided main system clock operation based on the subsystem clock selection of the main system or subsystem clock oscillator css0 0 1 divided output from the main system clock oscillator output form the subsystem clock oscillator caution bits 0, 1, 2, 3, 6, and 7 must be fixed to 0.
35 m pd789415, 789416, 789417 5.3 16-bit timer/counter 5.3.1 16-bit timer/counter functions the 16-bit timer/counter (tm5) has the following functions. (1) timer interrupt an interrupt is generated if the tm5 count matches a comparison value. (2) timer output the timer output can be controlled if the count matches a comparison value. (3) count capture the count in tm5 is captured into the capture register in synchronization with a capture trigger. 5.3.2 16-bit timer/counter configuration the 16-bit timer/counter (tm5) consists of the following hardware. table 5-5. 16-bit timer/counter configuration item configuration timer register 16 bits 1 (tm5) register compare register : 16 bits 1 (cr50) capture register : 16 bits 1 (tcp5) timer output 1 (to5) control register 16-bit timer mode control register 5 (tmc5) port mode register 2 (pm2) figure 5-11. 16-bit timer/counter block diagram cpt5/p27 /intp3 internal bus internal bus 16-bit timer mode control register 5 16-bit timer mode control register 5 tof5 cpt51 cpt50 toc5 tcl51 tcl50 toe5 selector f x f x /2 5 edge detection circuit 16-bit capture register 5 (tcp5) 16-bit counter read butter 16-bit timer register 5 (tm5) 16-bit compare register 5 (cr50) match ovf f/f tod5 to5/intp2 /p26 inttm5 p26 output latch pm26
36 m pd789415, 789416, 789417 (1) 16-bit compare register 5 (cr50) a value specified in cr50 is compared with the count in 16-bit timer register 5 (tm5). if they match, an interrupt request (inttm5) is issued. cr50 is set using an 8-bit or 16-bit memory manipulation instruction. any value from 0000h to ffffh can be set. a reset input loads ffffh into cr50. cautions 1. cr50 is designed to be manipulated using a 16-bit memory manipulation instruction. it can also be manipulated using 8-bit memory manipulation instructions, however. when an 8-bit memory manipulation instruction is used to set cr50, it must be in a direct addressing access mode. 2. to re-set cr50 during count operation, it is necessary to disable interrupts in advance, using an interrupt mask flag register (mk1). it is also necessary to disable inversion of the timer output data, using 16-bit timer mode control register 5 (tmc5). (2) 16-bit timer register 5 (tm5) tm5 is used to count the number of pulses. the contents of tm5 are read using an 8-bit or 16-bit memory manipulation instruction. a reset input clears tm5 to 0000h. cautions 1. the count becomes undefined when stop mode is deselected, because the count operation is performed before oscillation settles. 2. tm5 is designed to be manipulated using a 16-bit memory manipulation instruction. it can also be manipulated using 8-bit memory manipulation instructions, however. when an 8-bit memory instruction is used to manipulate tm5, it must be in a direct addressing access mode. 3. when an 8-bit memory manipulation instruction is used to manipulate tm5, the lower and upper bytes must be read as a pair, in this order. (3) 16-bit capture register 5 (tcp5) tcp5 captures the contents of 16-bit timer 5 (tm5). it is set using an 8-bit or 16-bit memory manipulation instruction. a reset input makes tcp5 undefined. caution tcp5 is designed to be manipulated using a 16-bit memory manipulation instruction. it can also be manipulated using 8-bit memory manipulation instructions, however. when an 8-bit memory manipulation instruction is used to manipulate tcp5, it must be in a direct addressing access mode. (4) 16-bit counter read buffer this buffer is used to latch and hold the count for 16-bit timer 5 (tm5).
37 m pd789415, 789416, 789417 5.3.3 16-bit timer/counter control registers the 16-bit timer/counter (tm5) is controlled by the following registers. ? 16-bit timer mode control register 5 (tmc5) ? port mode register 2 (pm2) (1) 16-bit timer mode control register 5 (tmc5) tmc5 controls the count clock and capture edge settings. tmc5 is set using a 1-bit or 8-bit memory manipulation instruction. a reset input clears tmc5 to 00h.
38 m pd789415, 789416, 789417 figure 5-12. 16-bit timer mode control register 5 format tod5 tod5 tof5 cpt51 cpt50 toc5 tcl51 tcl50 toe5 tmc5 symbol address when reset r/w ff48h 00h r/w note 1 5 6 43210 causes the 16-bit timer output data to be held. 7 tof5 0 1 overflow flag control reset or cleared by software set when the 16-bit timer overflows cpt51 0 0 1 1 capture edge selection cpt50 0 1 0 1 capture operation disabled captured at the rising edge at the cpt5 pin captured at the falling edge at the cpt5 pin captured at both the rising and falling edges at the cpt5 pin toc5 0 1 timer output data inversion control inversion disabled inversion enabled tcl51 0 0 16-bit timer register 5 count clock selection tcl50 0 1 f x (5.0 mhz) note 2 f x /2 5 (156.3 khz) note 3 not to be specified toe5 0 1 16-bit timer/counter 5 output control output disabled (port mode) output enabled other settings notes 1. bit 7 is read-only. 2. if the count clock is set to f x (tcl51 = 0, tcl50 = 0), the capture function cannot be used. to read the timer output, the cpu clock must be set to the main system clock high-speed mode (pcc1 = 0, css0 = 0). (see figure 5-8. ) 3. to read the timer output, the cpu clock must be set to the main system clock (pcc1 = 0, css0 = 0 or pcc1 = 1, css0 = 0). (see figure 5-8. ) remarks 1. f x : main system clock oscillation frequency 2. the parenthesized values apply to operation at f x = 5.0 mhz.
39 m pd789415, 789416, 789417 (2) port mode register 2 (pm2) pm2 specifies whether each bit of port 2 is used for input or output. to use the p26/intp2/to5 pin for timer output, the pm26 and p26 output latches must be reset to 0. pm2 is set using a 1-bit or 8-bit memory manipulation instruction. a reset input loads ffh into pm2. figure 5-13. port mode register 2 format pm27 pm26 pm25 pm24 pm23 pm22 pm21 pm20 pm2 symbol address when reset r/w ff22h ffh r/w 76543210 pm26 0 1 p26 pin input/output mode selection output mode (output buffer on) input mode (output buffer off)
40 m pd789415, 789416, 789417 5.4 8-bit timer/event counter 5.4.1 8-bit timer/event counter functions devices of the m pd789417 subseries have two timer/event counters (tm0 and tm1) and one timer counter (tm2). readers who are seeking a description of tm2 should read the term timer/event counter as timer counter. the 8-bit timer/event counters (tm0, tm1, and tm2) have the following functions. (1) 8-bit interval timer this timer causes interrupts to be issued at specified intervals. (2) external event counter (tm0 and tm1) this counter is used to count the number of pulses input from an external source. (3) square wave output (tm2 only) a square wave of any frequency can be output. table 5-6. 8-bit timer/event counter types and functions tm0 tm1 tm2 type interval timer one channel one channel one channel external event counter function timer output interrupt request 5.4.2 8-bit timer/event counter configuration the 8-bit timer/event counter consists of the following hardware. table 5-7. 8-bit timer/event counter configuration item configuration timer register 8 bits 3 (tm0, tm1, tm2) register compare registers: 8 bits 3 (cr00, cr10, cr20) timer output 1 (to2) control register 8-bit timer mode control registers 0, 1, 2 (tmc0, tmc1, tmc2) port mode register 2 (pm2)
41 m pd789415, 789416, 789417 figure 5-14. 8-bit timer/event counters 0 and 1 (tm0 and tm1) block diagram internal bus 8-bit compare register (crn0) match inttmn selector selector clear 8-bit timer register (tmn) 2 tcen tcln1 tcln0 8-bit timer mode control register n ? ? ? ? ? count clock note internal bus note f x /2 6 , f x /2 9 , ti0/p24/intp0 for tm0 f x /2 4 , f x /2 8 , ti1/p25/intp1 for tm1 remark n = 0 or 1
42 m pd789415, 789416, 789417 figure 5-15. 8-bit timer counter 2 (tm2) block diagram internal bus internal bus 8-bit compare register (cr20) match inttm2 f x /2 3 f x /2 7 f xt clear 8-bit timer register (tm2) to2/cmptout0/ p23 2 tce2 tcl21 tcl20 toe2 8-bit timer mode control register 2 f/f p23 output latch pm23 comparator note selector selector selector internal bus note see section 5.8 for details of the comparator. (1) 8-bit compare register n (crn0) a value specified in crn0 is compared with the count in 8-bit timer register n (tmn). if they match, an interrupt request (inttmn) is issued. crn0 is set using an 8-bit memory manipulation instruction. any value from 00h to ffh can be set. a reset input makes crn0 undefined. remark n = 0 to 2 (2) 8-bit timer register n (tmn) tmn is used to count the number of pulses. its contents are read using an 8-bit memory manipulation instruction. a reset input clears tmn to 00h. remark n = 0 to 2
43 m pd789415, 789416, 789417 5.4.3 8-bit timer/event counter control registers the 8-bit timer/event counter is controlled by the following registers. ? 8-bit timer mode control registers 0, 1, and 2 (tmc0, tmc1, and tmc2) ? port mode register 2 (pm2) (1) 8-bit timer mode control register 0 (tmc0) tmc0 determines whether to enable or disable 8-bit timer register 0 (tm0) and specifies the count clock for tm0. tmc0 is set using a 1-bit or 8-bit memory manipulation instruction. a reset input clears tmc0 to 00h. figure 5-16. 8-bit timer mode control register 0 format tce0 0000 tcl01 tcl00 0 tmc0 symbol address when reset r/w ff53h 00h r/w 6 7 543210 tcl01 0 0 1 1 8-bit timer register 0 count clock selection tcl00 0 1 0 1 f x /2 6 f x /2 9 rising edge of ti0 falling edge of ti0 tce0 0 1 8-bit timer register 0 operation control operation disabled (tm0 is cleared to 0.) operation enabled (78.1 khz) (9.77 khz) caution always stop the timer before setting tmc0. remarks 1. f x : main system clock oscillation frequency 2. the parenthesized values apply to operation at f x = 5.0 mhz.
44 m pd789415, 789416, 789417 (2) 8-bit timer mode control register 1 (tmc1) tmc1 determines whether to enable or disable 8-bit timer register 1 (tm1) and specifies the count clock for tm1. tmc1 is set using a 1-bit or 8-bit memory manipulation instruction. a reset input clears tmc1 to 00h. figure 5-17. 8-bit timer mode control register 1 format tce1 0000 tcl11 tcl10 0 tmc1 symbol address when reset r/w ff57h 00h r/w 6 7 543210 tcl11 0 0 1 1 8-bit timer register 1 count clock selection tcl10 0 1 0 1 f x /2 4 f x /2 8 rising edge of ti1 falling edge of ti1 tce1 0 1 8-bit timer register 1 operation control operation disabled (tm1 is cleared to 0.) operation enabled (312.5 khz) (19.5 khz) caution always stop the timer before setting tmc1. remarks 1. f x : main system clock oscillation frequency 2. the parenthesized values apply to operation at f x = 5.0 mhz.
45 m pd789415, 789416, 789417 (3) 8-bit timer mode control register 2 (tmc2) tmc2 determines whether to enable or disable 8-bit timer register 2 (tm2) and specifies the count clock for tm2. it also controls the operation of the output control circuit of 8-bit timer counter 2. tmc2 is set using a 1-bit or 8-bit memory manipulation instruction. a reset input clears tmc2 to 00h. figure 5-18. 8-bit timer mode control register 2 format tce2 0000 tcl21 tcl20 toe2 tmc2 symbol address when reset r/w ff5bh 00h r/w 6 70 54321 toe2 0 1 8-bit timer counter 2 output control output disabled (port mode) output enabled tcl21 0 0 1 1 8-bit timer register 2 count clock selection tcl20 0 1 0 1 f x /2 3 f x /2 7 f xt (32.768 khz) not to be specified tce2 0 1 8-bit timer register 2 operation control operation disabled (tm2 is cleared to 0.) operation enabled (625 khz) (39.1 khz) caution always stop the timer before setting tmc2. remarks 1. f x : main system clock oscillation frequency 2. f xt : subsystem clock oscillation frequency 3. the parenthesized values apply to operation at f x = 5.0 mhz or f xt = 32.768 khz.
46 m pd789415, 789416, 789417 (4) port mode register 2 (pm2) pm2 specifies whether each bit of port 2 is used for input or output. to use the p23/cmptout0/to2 pin for timer output, the pm23 and p23 output latches must be reset to 0. pm2 is set using a 1-bit or 8-bit memory manipulation instruction. a reset input loads ffh into pm2. figure 5-19. port mode register 2 format pm23 0 1 p23 pin input/output mode selection output mode (output buffer on) input mode (output buffer off) pm27 pm26 pm25 pm24 pm23 pm22 pm21 pm20 pm2 7654 symbol address when reset r/w ff22h ffh r/w 3210
47 m pd789415, 789416, 789417 5.5 clock timer 5.5.1 clock timer functions the clock timer has the following functions. ? clock timer ? interval timer the clock and interval timers can be used at the same time. figure 5-20 is a block diagram of the clock timer. figure 5-20. clock timer block diagram f x /2 7 f xt f w f w 2 4 f w 2 5 f w 2 6 f w 2 7 f w 2 8 f w 2 9 clear 9-bit prescaler selecter clear 5-bit counter intwt intwti wtm7 wtm6 wtm5 wtm4 0 wtm1 wtm0 clock timer mode control register (wtm) internal bus selecter
48 m pd789415, 789416, 789417 (1) clock timer the 4.19-mhz main system clock or 32.768-khz subsystem clock is used to issue an interrupt request (intwt) at 0.5-second intervals. caution when the main system clock is operating at 5.0 mhz, it cannot be used to generate a 0.5-second interval. in this case, the subsystem clock, which operates at 32.768 khz, should be used instead. (2) interval timer the interval timer is used to generate an interrupt request (intwt) at specified intervals. table 5-8. interval generated using the interval timer interval operation at f x = 5.0 mhz operation at f x = 4.19 mhz operation at f xt = 32.768 khz 2 4 1/f w 409.6 m s 489 m s 488 m s 2 5 1/f w 819.2 m s 978 m s 977 m s 2 6 1/f w 1.64 ms 1.96 ms 1.95 ms 2 7 1/f w 3.28 ms 3.91 ms 3.91 ms 2 8 1/f w 6.55 ms 7.82 ms 7.81 ms 2 9 1/f w 13.1 ms 15.6 ms 15.6 ms remark f w : clock timer clock frequency (f x /2 7 or f xt ) f x : main system clock oscillation frequency f xt : subsystem clock oscillation frequency 5.5.2 clock timer configuration the clock timer consists of the following hardware. table 5-9. clock timer configuration item configuration counter 5 bits prescaler 9 bits control register clock timer mode control register (wtm)
49 m pd789415, 789416, 789417 5.5.3 register for controlling the clock timer the clock timer mode control register (wtm) is used to control the clock timer. ? clock timer mode control register (wtm) the wtm selects a count clock for the clock timer and specifies whether to enable clocking of the timer. it also specifies the prescaler interval and how the 5-bit counter is controlled. the wtm is manipulated using a 1-bit or 8-bit memory manipulation instruction. a reset input clears the wtm to 00h. figure 5-21. clock timer mode control register format clock timer count clock selection wtm7 wtm6 wtm5 wtm4 0 0 wtm1 wtm0 wtm symbol address when reset r/w ff4ah 00h r/w 76543210 wtm7 0 1 prescaler interval selection wtm6 0 0 0 0 1 1 2 4 /f w 2 5 /f w 2 6 /f w 2 7 /f w 2 8 /f w 2 9 /f w wtm5 0 0 1 1 0 0 (488 s) (977 s) (1.95 ms) (3.91 ms) (7.81 ms) (15.6 ms) m m wtm4 0 1 0 1 0 1 control of 5-bit counter operation wtm1 0 1 cleared after stop started clock timer operation wtm0 0 1 operation disabled (both prescaler and timer cleared) operation enabled other settings f x /2 7 f xt (39.1 khz) (32.768 khz) not to be set remarks 1. f w : clock timer clock frequency (f x /2 7 or f xt ) 2. f x : main system clock oscillation frequency 3. f xt : subsystem clock oscillation frequency 4. the parenthesized values apply to operation at f x = 5.0 mhz or f w = 32.768 khz.
50 m pd789415, 789416, 789417 5.6 watchdog timer 5.6.1 watchdog timer functions the watchdog timer has the following functions. (1) watchdog timer the watchdog timer is used to detect unintended program loops. if an unintended program loop is detected, a nonmaskable interrupt or reset signal is generated. (2) interval timer the interval timer is used to generate interrupts at specified intervals. 5.6.2 watchdog timer configuration the watchdog timer consists of the following hardware. table 5-10. watchdog timer configuration item configuration control register timer clock selection register 2 (tcl2) watchdog timer mode register (wdtm)
51 m pd789415, 789416, 789417 figure 5-22. watchdog timer block diagram internal bus internal bus prescaler f x 2 6 f x 2 8 f x 2 10 3 7-bit counter run clear tmif4 tmmk4 tcl22 tcl21 tcl20 timer clock selection register 2 watchdog timer mode register wdtm4 wdtm3 intwdt maskable interrupt request reset intwdt nonmaskable interrupt request f x 2 4 selector control circuit
52 m pd789415, 789416, 789417 5.6.3 watchdog timer control registers the watchdog timer is controlled by the following registers. ? timer clock selection register 2 (tcl2) ? watchdog timer mode register (wdtm) (1) timer clock selection register 2 (tcl2) tcl2 specifies the count clock for the watchdog timer. tcl2 is set using an 8-bit memory manipulation instruction. a reset input clears tcl2 to 00h. figure 5-23. timer clock selection register 2 format tcl22 0 0 1 1 watchdog timer count clock selection interval time 00000 tcl22 tcl21 tcl20 tcl2 symbol address when reset r/w ff42h 00h r/w 76543210 tcl21 0 1 0 1 f x /2 4 f x /2 6 f x /2 8 f x /2 10 not to be specified (312.5 khz) (78.1 khz) (19.5 khz) (4.88 khz) (410 s) (1.64 ms) (6.55 ms) (26.2 ms) m other settings tcl20 0 0 0 0 2 11 /f x 2 13 /f x 2 15 /f x 2 17 /f x remarks 1. f x : main system clock oscillation frequency 2. the parenthesized values apply to operation at f x = 5.0 mhz.
53 m pd789415, 789416, 789417 (2) watchdog timer mode register (wdtm) the wdtm specifies the watchdog timer operation mode and whether to enable or disable counting. the wdtm is set using a 1-bit or 8-bit memory manipulation instruction. a reset input clears the wdtm to 00h. figure 5-24. watchdog timer mode register format run 0 1 watchdog timer operation selection note 1 run 0 0 wdtm4 wdtm3 000 wdtm symbol address when reset r/w fff9h 00h r/w 6 7 543210 stops counting. clears the counter and causes it start. wdtm4 0 0 1 1 watchdog timer operation mode selection note 2 wdtm3 0 1 0 1 operation disabled internal timer mode (when an overflow occurs, a maskable interrupt is issued.) note 3 watchdog timer mode 1 (when an overflow occurs, a nonmaskable interrupt is issued.) watchdog timer mode 2 (when an overflow occurs, a reset operation is started.) notes 1. once the run bit has been set (1), it is impossible to zero-clear it by software. so, once counting begins, it cannot be stopped by any means other than a reset input. 2. once wdtm3 and wdtm4 have been set (1), it is impossible to zero-clear them by software. 3. the interval timer starts operating when the run bit is set to 1. cautions 1. if the run bit is set to 1, and the watchdog timer is cleared, the actual overflow time becomes 0.8 % (maximum) less than the time specified in timer clock selection register 2. 2. to use watchdog timer mode 1 or 2, ensure that the interrupt request flag (tmif4) is set to 0, before setting wdtm4 to 1. if tmif4 is set to 1, selecting mode 1 or 2 causes a nonmaskable interrupt to be issued at the instant rewriting ends.
54 m pd789415, 789416, 789417 5.7 10-bit a/d converter 5.7.1 10-bit a/d converter functions the 10-bit a/d converter converts input analog voltages to digital signals with an 10-bit resolution. it can control up to seven analog input channels (ani0 to ani6). a/d conversion can be started only by software. one of analog inputs ani0 to ani6 is selected for a/d conversion. a/d conversion is performed repeatedly, with an interrupt request (intad) being issued each time an a/d session is completed. 5.7.2 configuration of the 10-bit a/d converter the a/d converter consists of the following hardware. table 5-11. 10-bit a/d converter configuration item configuration analog input 7 channels (ani0 to ani6) register successive approximation register (sar) a/d conversion result register (adcr) control register a/d converter mode register (adm) a/d input selection register (ads)
55 m pd789415, 789416, 789417 figure 5-25. a/d converter block diagram ani0 ani1 ani2 ani3 ani4 ani5 ani6 sample-and-hold circuit voltage comparator control circuit successive approximation register (sar) 3 a/d conversion result register (adcr) tap selector selector av ss intad a/d conveter mode register a/d input selection register internal bus av ss adcs 0 fr2 fr1 fr0 0 0 0 ads2 ads1 ads0 av ref av dd (1) successive approximation register (sar) the sar receives the result of comparing an analog input voltage and a voltage at a voltage tap (comparison voltage), received from the serial resistor string, starting from the most significant bit (msb). upon receiving all the bits, down to the least significant bit (lsb), that is, upon the completion of a/d conversion, the sar sends its contents to the a/d conversion result register. (2) a/d conversion result register (adcr) the adcr holds the result of a/d conversion. each time a/d conversion ends, the conversion result received from the successive approximation register is loaded into the adcr. the adcr can be manipulated using a 16-bit memory manipulation instruction. the value of this register becomes unpredictable upon the input of a reset signal. caution when read with an 8-bit memory manipulation instruction, the eight high-order bits of the 10-bit conversion result are read. (3) sample-and-hold circuit the sample-and-hold circuit samples consecutive analog inputs from the input circuit, one by one, and sends them to the voltage comparator. the sampled analog input voltage is held during a/d conversion. (4) voltage comparator the voltage comparator compares an analog input with the voltage output by the serial resistor string.
56 m pd789415, 789416, 789417 (5) serial resistor string the serial resistor string is configured between av ref and av ss . it generates the reference voltages against which analog inputs are compared. (6) ani0 to ani6 pins pins ani0 to ani6 are analog input pins for the a/d converter. they are used to receive the analog signals to be subject to a/d conversion. caution do not supply pins ani0 to ani6 with voltages that fall outside the rated range. if a voltage greater than av ref or less than av ss (even if within the absolute maximum rating) is supplied to any of these pins, the conversion value for the corresponding channel will be undefined. furthermore, the conversion values for the other channels may also be affected. (7) av ref pin the av ref pin is a reference voltage pin for the a/d converter. signals received at pins ani0 to ani6 are converted to digital signals while referencing the voltage across the av ref and av ss pins. (8) av ss pin the av ss pin is a ground potential pin for the a/d converter. this pin must be held at the same potential as the v ss0 pin, even while the a/d converter is not being used. (9) av dd pin the av dd pin is an analog power supply pin for the a/d converter. this pin must be held at the same potential as the v dd0 pin, even while the a/d converter is not being used.
57 m pd789415, 789416, 789417 5.7.3 10-bit a/d converter control registers the following two registers are used to control the 10-bit a/d converter. ? a/d converter mode register (adm) ? a/d input selection register (ads) (1) a/d converter mode register (adm) the adm specifies the conversion time for analog inputs. it also specifies whether to enable conversion. the adm can be manipulated using a 1-bit or 8-bit memory manipulation instruction. a reset input clears the adm to 00h. figure 5-26. a/d converter mode register format a/d conversion control adcs 0 fr2 fr1 fr0 0 0 0 adm symbol address when reset r/w ff80h 00h r/w 76543210 adcs 0 1 a/d conversion time selection note 1 fr2 0 0 0 1 1 1 144/fx 120/fx 96/fx 72/fx 60/fx 48/fx fr1 0 0 1 0 0 1 (28.8 s) (24 s) (19.2 s) (14.4 s) (not to be set note 2 ) (not to be set note 2 ) m m m fr0 0 1 0 0 1 0 other settings conversion disabled conversion enabled not to be set m notes 1. the specifications of fr2, fr1, and fr0 must be such that the a/d conversion time is at least 14 m s. 2. these bit combinations must not be used, as the a/d conversion time will fall below 14 m s. caution the result of conversion performed immediately after bit 7 (adcs) is set is undefined. remarks 1. f x : main system clock oscillation frequency 2. the parenthesized values apply to operation at f x = 5.0 mhz.
58 m pd789415, 789416, 789417 (2) a/d input selection register (ads) the ads register specifies the port used to input the analog voltages to be converted to a digital signal. the ads can be manipulated using a 1-bit or 8-bit memory manipulation instruction. a reset input clears the ads to 00h. figure 5-27. a/d input selection register format 00000 ads2 ads1 ads0 ads symbol address when reset r/w ff84h 00h r/w 76543210 analog input channel specification ads2 0 0 0 0 1 1 1 1 ani0 ani1 ani2 ani3 ani4 ani5 ani6 not to be set ads1 0 0 1 1 0 0 1 1 ads0 0 1 0 1 0 1 0 1
59 m pd789415, 789416, 789417 5.8 comparator 5.8.1 comparator functions the comparator has the following functions. (1) input voltage comparison the comparator compares an input voltage at the reference voltage input pin (cmpref0) with an input voltage at the comparator input pin (cmpin0). the comparison result can be read using memory manipulation instructions. (2) interrupt generation the comparator output (selectable with a rising and/or falling edge) is used to generate an interrupt request signal (intcmp). (3) clock output when cmpref0 > cmpin0, the output of 8-bit timer counter 2 (tm2) is directed to the cmptout0 pin. (4) open-drain output selection comparator mode register 0 (cmprm0) is used to specify a port as an n-ch open-drain output. 5.8.2 comparator configuration the comparator consists of the following hardware. (1) cmpin0 this is the comparator input pin. (2) cmptout0 this is the comparator output pin. (3) cmpref0 this is the comparator reference voltage input pin. figure 5-28 is a block diagram of the comparator.
60 m pd789415, 789416, 789417 figure 5-28. comparator block diagram internal bus p23 output latch pm23 cmptout0/p23 /to2 e + cmpin0 cmpref0 intcmp selector timing control cmpon selcmp opdr cmpout comparator mode register 8-bit timer 2 (tm2) output internal bus
61 m pd789415, 789416, 789417 5.8.3 comparator control register the comparator is controlled by the following register. (1) comparator mode register 0 (cmprm0) cmprm0 controls the power supply and output of the comparator. it also selects an open drain output for the comparator. cmprm0 is set using a 1-bit or 8-bit memory manipulation instruction. a reset input clears cmprm0 to 00h. figure 5-29. comparator mode register 0 format cmpon 0 1 comparator power supply on/off control 000 cmpon selcmp opdr cmpout cmprm0 symbol address when reset r/w ff4eh 00h r/w note 6 7 543210 selcmp 0 1 clock output control opdr 0 1 open-drain output selection cmpout 0 comparator power supply off comparator power supply on 8-bit timer counter (tm2) output 8-bit timer counter 2 (tm2) output if cmpref0 > cmpin0 cmos output n-ch open-drain output the comparator output is read. note bit 0 is read-only. cautions 1. bits 4 to 7 must be fixed to 0. 2. if the comparator is enabled (cmpon = 1), noise may be induced. if it is necessary to generate an interrupt request signal (intcmp) from the output of the comparator, enable the comparator (cmpon = 1) then clean the interrupt request flag (cmpif) to 0, before enabling interrupts. 3. similarly, if it is necessary to direct the output of the comparator to the port, enable the comparator (cmpon = 1) in advance.
62 m pd789415, 789416, 789417 5.9 serial interface channel 0 5.9.1 functions of serial interface channel 0 serial interface channel 0 has the following three modes. ? operation stopped mode ? asynchronous serial interface (uart) mode ? three-wire serial i/o mode (1) operation stopped mode this mode is used when serial transfer is not performed. power consumption is minimized in this mode. (2) asynchronous serial interface (uart) mode this mode is used to send and receive the one byte of data that follows a start bit. it supports full-duplex communication. serial interface channel 0 contains a dedicated uart baud rate generator, enabling communication over a wide range of baud rates. it is also possible to define baud rates by dividing the frequency of the input clock pulse at the asck pin. (3) three-wire serial i/o mode (switchable between msb-first and lsb-first transmission) this mode is used to transmit 8-bit data, using three lines: a serial clock (sck) line and two serial data lines (si and so). as it supports simultaneous transmission and reception, three-wire serial i/o mode requires less processing time for data transmission than asynchronous serial interface mode. because, in three-wire serial i/o mode, it is possible to select whether 8-bit data transmission begins with the msb or lsb, channel 0 can be connected to any device regardless of whether that device is designed for msb- first or lsb-first transmission. three-wire serial i/o mode is useful for connecting peripheral i/o circuits and display controllers having conventional clock synchronous serial interfaces, such as those of the 75x/xl, 78k, and 17k series devices. 5.9.2 serial interface channel 0 configuration serial interface channel 0 consists of the following hardware. table 5-12. serial interface channel 0 configuration item configuration register transmission shift register (txs) reception shift register (rxs) reception buffer register (rxb) control register serial operation mode register 0 (csim0) asynchronous serial interface mode register (asim) asynchronous serial interface status register (asis) baud rate generator control register (brgc)
63 m pd789415, 789416, 789417 internal bus reception shift register (rxs) reception buffer register (rxb/sio0) pe fe ove reception control circuit asynchronous serial interface status register intsr/intcsi0 direction control circuit direction control circuit transmission shift register (txs/sio0) transmission control circuit rxd/si/p22 txd/so/p21 pm21 pm20 txe rxe ps1 ps0 cl sl sck output control circuit baud rate generator note intst csie0 dir0 csck asynchronous serial interface mode register tps3 tps2 tps1 tps0 4 csie0 txe rxe csck serial operation mode register 0 baud rate generator control register asck/sck/p20 f x /2-f x /2 8 internal bus figure 5-30. serial interface channel 0 block diagram note see figure 5-31 for the configuration of the baud rate generator.
64 m pd789415, 789416, 789417 internal bus prescaler f x 2 f x 2 2 f x 2 3 f x 2 4 f x 2 5 f x 2 6 f x 2 7 f x 2 8 tps3 tps2 tps1 tps0 4 baud rate generator control register stop csie0 txe rxe f x /2 5 f x /2 asck/sck/p20 3-bit counter selector selector selector 3-bit counter brgc write txe clear clear 1/2 transmission clock 1/2 clear csie0 rxe csie0 csck reception clock clear rxe start bit detection brgc write figure 5-31. baud rate generator block diagram
65 m pd789415, 789416, 789417 (1) transmission shift register (txs) the txs is a register in which transmission data is prepared. the transmission data is output from the txs bit-serially. when the data length is seven bits, bits 0 to 6 of the data in the txs will be transmission data. writing data to the txs triggers transmission. the txs can be write-accessed, using an 8-bit memory manipulation instruction, but cannot be read-accessed. a reset input loads ffh into the txs. caution do not write to the txs during transmission. the txs and the reception buffer register (rxb) are mapped at the same address, such that any attempt to read from the txs results in a value being read from the rxb. (2) reception shift register (rxs) the rxs is a register in which serial data, received at the rxd pin, is converted to parallel data. once one entire byte has been received, the rxs feeds the reception data to the reception buffer register (rxb). the rxs cannot be manipulated directly by a program. (3) reception buffer register (rxb) the rxb is used to hold reception data. once the rxs has received one entire byte of data, it feeds that data into the rxb. when the data length is seven bits, the reception data is sent to bits 0 to 6 of the rxb, in which the msb is fixed to 0. the rxb can be read-accessed, using an 8-bit memory manipulation instruction, but cannot be write-accessed. a reset input makes the rxb undefined. caution the rxb and the transmission shift register (txs) are mapped at the same address, such that any attempt to write to the rxb results in a value being written to the txs. (4) transmission control circuit the transmission control circuit controls transmission. for example, it adds start, parity, and stop bits to the data in the transmission shift register (txs), according to the setting of the asynchronous serial interface mode register (asim). (5) reception control circuit the reception control circuit controls reception according to the setting of the asynchronous serial interface mode register (asim). it also checks for errors, such as parity errors, during reception. if an error is detected, the asynchronous serial interface status register (asis) is set according to the status of the error.
66 m pd789415, 789416, 789417 5.9.3 serial interface channel 0 control registers serial interface channel 0 is controlled by the following registers. ? serial operation mode register 0 (csim0) ? asynchronous serial interface mode register (asim) ? asynchronous serial interface status register (asis) ? baud rate generator control register (brgc) (1) serial operation mode register 0 (csim0) csim0 is used to make the settings related to three-wire serial i/o mode. csim0 is set using a 1-bit or 8-bit memory manipulation instruction. a reset input clears csim0 to 00h. figure 5-32. serial operation mode register 0 format csie0 0 1 three-wire serial i/o mode operation control csie0 0000 dir0 csck 0 csim0 symbol address when reset r/w ff72h 00h r/w 6 7 543210 operation disabled operation enabled dir0 0 1 first-bit specification msb lsb csck 0 1 three-wire serial i/o mode clock selection external clock pulse input to the sck0 pin output of the dedicated baud rate generator cautions 1. bit 0 and bits 3 to 6 must be fixed to 0. 2. csim0 must be cleared to 00h, if uart mode is selected.
67 m pd789415, 789416, 789417 (2) asynchronous serial interface mode register (asim) the asim is used to make the settings related to asynchronous serial interface mode. the asim is set using a 1-bit or 8-bit memory manipulation instruction. a reset input clears the asim to 00h. figure 5-33. asynchronous serial interface mode register format txe 0 1 transmission control txe rxe ps1 ps0 cl sl 0 0 asim symbol address when reset r/w ff70h 00h r/w 5 6 7 43210 transmission disabled transmission enabled rxe 0 1 reception control reception disabled reception enabled ps1 0 0 1 1 parity bit specification ps0 0 1 0 1 no parity at transmission, the parity bit is fixed to 0. at reception, a parity check is not made; no parity error is reported. odd parity even parity cl 0 1 character length specification 7 bits 8 bits sl 0 1 transmission data stop bit length 1 bit 2 bits cautions 1. bits 0 and 1 must be fixed to 0. 2. if three-wire serial i/o mode is selected, the asim must be cleared to 00h. 3. before switching from one mode to another, stop both serial transmission and reception.
68 m pd789415, 789416, 789417 table 5-13. serial interface channel 0 operation mode settings (1) operation stopped mode asim csim0 txe rxe csie0 dir0 csck 000 note 1 note 1 note 1 note 1 note 1 note 1 -- p22 p21 p20 other settings not to be specified (2) three-wire serial i/o mode asim csim0 txe rxe csie0 dir0 csck 001001 note 2 note 2 011 msb external clock si0 note2 so0 (cmos output) sck0 input 1 0 1 internal clock sck0 output 110 1 lsb external clock sck0 input 1 0 1 internal clock sck0 output other settings not to be specified (3) asynchronous serial interface mode asim csim0 txe rxe csie0 dir0 csck 10000 note 1 note 1 011 lsb external clock p22 txd (cmos output) asck input note 1 note 1 internal clock p20 010001 note 1 note 1 1 external clock rxd p21 asck input note 1 note 1 internal clock p20 110001 011 external clock txd (cmos output) asck input note 1 note 1 internal clock p20 other settings not to be specified notes 1. these pins can be used for port functions. 2. when only transmission is used, these pins can be used as p22 (cmos input/output). remark : dont care. first bit p20 pm20 p21 pm21 p22 pm22 p22/si/rxd pin function shift clock p21/so/txd pin function p20/sck/ asck pin function p21/so/txd pin function p21/so/txd pin function shift clock shift clock p20/sck/ asck pin function p20/sck/ asck pin function p20 p20 pm20 pm20 p21 p21 pm21 pm21 p22 p22 pm22 pm22 first bit first bit p22/si/rxd pin function p22/si/rxd pin function
69 m pd789415, 789416, 789417 (3) asynchronous serial interface status register (asis) the asis is used to display the type of a reception error, if it occurs while asynchronous serial interface mode is set. the asis is set using an 8-bit memory manipulation instruction. the contents of the asis are undefined in three-wire serial i/o mode. a reset input clears the asis to 00h. figure 5-34. asynchronous serial interface status register format pe 0 1 parity error flag 00000pefeove asis symbol address when reset r/w ff71h 00h r 76543210 no parity error has occurred. a parity error has occurred (parity mismatch in transmission data). fe 0 1 framing error flag no framing error has occurred. a framing error has occurred (no stop bit detected). note 1 ove 0 1 overrun error flag no overrun error has occurred. an overrun error has occurred. note 2 (before data was read from the reception buffer register, the subsequent reception sequence was completed.) notes 1. even if 2 is specified for the number of stop bits (using bit 2 (sl) of the asim), only one stop bit is detected at reception. 2. after an overrun occurs, read-access the reception buffer register (rxb). otherwise, the overrun error will recur each time data is received.
70 m pd789415, 789416, 789417 (4) baud rate generator control register (brgc) the brgc is used to specify the serial clock for serial interface channel 0. the brgc is set using an 8-bit memory manipulation instruction. a reset input clears the brgc to 00h. figure 5-35. baud rate generator control register format tps3 0 0 0 0 0 0 0 0 1 3-bit counter source clock selection tps3 tps2 tps1 tps0 0000 brgc symbol address when reset r/w ff73h 00h r/w 76543210 tps2 0 0 0 0 1 1 1 1 0 f x /2 f x /2 2 f x /2 3 f x /2 4 f x /2 5 f x /2 6 f x /2 7 f x /2 8 external clock pulse input at the asck pin note not to be specified (2.5 mhz) (1.25 mhz) (625 khz) (313 khz) (156 khz) (78.1 khz) (39.1 khz) (19.5 khz) other settings tps1 0 0 1 1 0 0 1 1 0 tps0 0 1 0 1 0 1 0 1 0 n 1 2 3 4 5 6 7 8 note an external clock can be used only in uart mode. cautions 1. any attempt to write to the brgc during communication adversely affects the output of the baud rate generator, thus hampering normal operation. therefore, do not write to the brgc during communication. 2. do not select n = 1 during operation at f x = 5.0 mhz, as n = 1 causes the rated baud rate to be exceeded. remarks 1. f x : main system clock oscillation frequency 2. n : value specified in tps0 to tps3 (1 n 8) 3. the parenthesized values apply to operation at f x = 5.0 mhz.
71 m pd789415, 789416, 789417 the transmission and reception clock pulses used to generate the baud rate are obtained by dividing the frequency of the main system clock pulse or a signal input to the asck pin. (a) generating transmission and reception clock pulses for baud rates based on the main system clock the frequency of the main system clock is divided to generate the transmission and reception clock pulses. the baud rate generated based on the main system clock is determined using the following expression. [baud rate] = [hz] f x : main system clock oscillation frequency n : value specified at tps0 to tps3 (2 n 8) table 5-14. relationships between main system clock frequencies and baud rates (example) error (%) fx = 5.0 mhz fx = 4.9152 mhz 1 200 70h 1.73 0 2 400 60h 4 800 50h 9 600 40h 19 200 30h 38 400 20h 76 800 10h baud rate (bps) brgc setting f x 2 n+1 8
72 m pd789415, 789416, 789417 (b) generating transmission and reception clock pulses for baud rates based on an external clock pulse received at the asck pin the frequency of an external clock pulse received at the asck pin is used to generate the transmission and reception clock pulses. the baud rate generated based on the external clock pulse received at the asck pin is determined using the following expression. [baud rate] = [hz] f asck : frequency of clock pulse received at the asck pin table 5-15. relationships between asck pin input frequencies and baud rates (when brgc = 80h) baud rate (bps) asck pin input frequency (khz) 75 1.2 150 2.4 300 4.8 600 9.6 1 200 19.2 2 400 38.4 4 800 76.8 9 600 153.6 19 200 307.2 31 250 500.0 38 400 614.4 f asck 16
73 m pd789415, 789416, 789417 5.10 lcd controller/driver 5.10.1 lcd controller/driver functions the functions of the lcd controller/driver of the m pd789415, m pd789416, and m pd789417 are as follows: (1) automatic output of segment and common signals based on automatic display data memory read (2) five different display modes: ? static ? 1/2 duty (1/2 bias) ? 1/3 duty (1/2 bias) ? 1/3 duty (1/3 bias) ? 1/4 duty (1/3 bias) (3) four different frame frequencies, selectable in each display mode (4) up to 28 segment signal outputs (s0 to s27) and four common signal outputs (com0 to com3) of these segment signal outputs, 12 outputs can be switched to input/output ports in 2-output units (p80/s27 to p87/s20 and p90/s19 to p93/s16). (5) voltage divider resistors (for lcd drive voltage generation) that a port itself can contain if so specified with a mask option (6) operation with a subsystem clock table 5-16 lists the maximum number of pixels that can be displayed in each display mode. table 5-16. maximum number of pixels bias mode number of time slices common signals used maximum number of pixels - static com0 (com1-com3) 28 (28 segment signals, 1 common signal) note 1 1/2 2 com0, com1 56 (28 segment signals, 2 common signals) note 2 3 com0-com2 84 (28 segment signals, 3 common signals) note 3 1/3 3 com0-com2 4 com0-com3 112 (28 segment signals, 4 common signals) note 4 notes 1. three-digit lcd panel, each digit having an 8-segment configuration. 2. seven-digit lcd panel, each digit having a 4-segment configuration. 3. nine-digit lcd panel, each digit having a 3-segment configuration. 4. fourteen-digit lcd panel, each digit having a 2-segment configuration.
74 m pd789415, 789416, 789417 5.10.2 lcd controller/driver configuration the lcd controller/driver consists of the following hardware. table 5-17. lcd controller/driver configuration item configuration display output 28 segment signals (16 dedicated segment signals and 12 segment and input/output port signals) 4 common signals (com0 to com3) control register lcd display mode register (lcdm) lcd port selector (lps) lcd clock control register (lcdc)
75 m pd789415, 789416, 789417 internal bus lcd clock control register (lcdc) lcdc3 lcdc2 lcdc1 lcdc0 2 2 lcd display mode register (lcdh) lcd port selector (lps) 3 selector prescaler segment selector lcd clock selector selector selector selector lcd drive voltage controller common driver f lcd f lcd 2 6 f lcd 2 7 f lcd 2 8 f lcd 2 9 lps5 lcdon vaon lips lcdm2 lcdm1 lcdm0 lcs4 lps3 lps2 lps1 lps0 6 v lc2 s /p8 v lc1 v lc0 bias p8 output buffer segment driver segment driver segment driver p9 output buffer com0 com1 com2 com3 3210 3210 65 74 f h display data memory lcdon s /p9 3210 3210 65 74 f h lcdon 3210 3210 65 74 f h p8 output latch lcdon s p9 output latch timing controller f x /2 7 f xt figure 5-36. lcd controller/driver block diagram
76 m pd789415, 789416, 789417 5.10.3 lcd controller/driver control registers the following three types of registers are used to control the lcd controller/driver. ? lcd display mode register (lcdm) ? lcd port selector (lps) ? lcd clock control register (lcdc) (1) lcd display mode register (lcdm) the lcdm specifies whether to enable display operation. it also specifies the operation mode, lcd drive power supply, and display mode. the lcdm is manipulated using a 1-bit or 8-bit memory manipulation instruction. a reset clears the lcdm to 00h. figure 5-37. lcd display mode register format lcdon vaon 0 lips 0 lcdm2 lcdm1 lcdm0 lcdm symbol address when reset r/w ffb0h 00h r/w 76543210 lcd controller/driver display mode selection lcdm2 0 0 0 0 1 4 3 2 3 static not to be set lcdm1 0 0 1 1 0 lcdm0 0 1 0 1 0 control of lcd display lcdon 0 1 display off (all segment outputs are deselected.) display on lcd drive power supply selection lips 0 1 lcd controller/driver operation mode note vaon 0 1 normal operation low-voltage operation lcd drive power is not supplied. lcd drive power is supplied to the bias pin. number of time slices bias mode 1/3 1/3 1/2 1/2 other settings note when the lcd display panel is not used, vaon and lips must be fixed to 0 to conserve power. caution before attempting to manipulate vaon, set lips and lcdon to 0 to turn off the lcd.
77 m pd789415, 789416, 789417 (2) lcd port selector (lps) the lps controls port and segment signal output switching. the lps is manipulated using a 1-bit or 8-bit memory manipulation instruction. a reset clears the lps to 00h. figure 5-38. lcd port selector format 0 lps0 lps symbol address when reset r/w ffb1h 00h r/w 76543210 0 1 used as ports (pmn) lps4 lps3 lps2 lps1 lps0 p93/s16, p92/s17 p91/s18, p90/s19 p87/s20, p86/s21 p85/s22, p84/s23 p83/s24, p82/s25 p81/s26, p80/s27 used as segments (s ) lps5 lps1 lps2 lps4 lps5 0 lps3 remark m = 8 n = 0 to 7 m = 9 n = 0 to 3 = 16 to 27
78 m pd789415, 789416, 789417 (3) lcd clock control register (lcdc) the lcdc specifies the lcd clock and frame frequency. the lcdc is manipulated using a 1-bit or 8-bit memory manipulation instruction. a reset clears the lcdc to 00h. figure 5-39. lcd clock control register format lcdc3 lcdc2 lcdc1 lcdc0 lcdc symbol address when reset r/w ffb2h 00h r/w 76543210 lcd clock (f lcd ) selection note lcdc3 0 0 1 1 lcdc2 0 1 0 1 lcd frame frequency selection lcdc1 0 0 1 1 lcdc0 0 1 0 1 0000 f lcd /2 6 f lcd /2 7 f lcd /2 8 f lcd /2 9 f x /2 7 f xt not to be set note specify an lcd clock (f lcd ) frequency of at least 32 khz. table 5-18 lists the frame frequencies used when f xt (32.768 khz) is supplied to the lcd clock (f lcd ). table 5-18. frame frequencies (hz) frame frequency display duty ratio f xt /2 9 (64 hz) f xt /2 8 (128 hz) f xt /2 7 (256 hz) f xt /2 6 (512 hz) static 64 128 256 512 1/2 32 64 128 256 1/3 21 43 85 171 1/4 16 32 64 128 remark the parenthesized values apply when f xt (32.768 khz) is supplied to the lcd clock (f lcd ).
79 m pd789415, 789416, 789417 6. interrupt functions 6.1 interrupt function types two types of interrupt function are supported. (1) nonmaskable interrupt a nonmaskable interrupt request is accepted unconditionally, that is, even when interrupts are disabled. a nonmaskable interrupt takes precedence over all other interrupts; it is not subjected to interrupt priority control. a nonmaskable interrupt causes the standby release signal to be generated. the m pd789415, m pd789416, and m pd789417 support one nonmaskable interrupt source namely, the watchdog timer interrupt. (2) maskable interrupt maskable interrupts are those which are subjected to mask control. if two or more maskable interrupts occur simultaneously, the default priority listed in table 6-1 applies. the maskable interrupts cause the standby release signal to be generated. the maskable interrupts supported by the m pd789415, m pd789416, and m pd789417 include 4 external interrupt sources and 12 internal interrupt sources. 6.2 interrupt sources and configuration the m pd789415, m pd789416, and m pd789417 each support a total of 17 maskable and nonmaskable interrupt sources. (see table 6-1 .)
80 m pd789415, 789416, 789417 table 6-1. interrupt sources interrupt type default priority note 1 interrupt source internal/external name trigger nonmaskable interrupt - intwdt watchdog timer overflow (when watchdog timer mode 1 is selected) internal 0004h (a) maskable 0 intwdt watchdog timer overflow (when the interval timer mode is selected) (b) 1 intp0 pin input edge detection external 0006h (c) 2 intp1 0008h 3 intp2 000ah 4 intp3 000ch 5 intsr end of uart reception on serial interface channel 0 internal 000eh (b) intcsi0 end of three-wire sio transfer reception on serial interface channel 0 6 intst end of uart transmission on serial interface channel 0 0010h 7 intwt clock timer interrupt 0012h 8 intwti interval timer interrupt 0014h 9 inttm0 generation of match signal for 8-bit timer/event counter 0 0016h 10 inttm1 generation of match signal for 8-bit timer/event counter 1 0018h 11 inttm2 generation of match signal for 8-bit timer counter 2 001ah 12 inttm5 generation of match signal for 16- bit timer counter 5 001ch 13 intkr key return signal detection 001eh 14 intad a/d conversion completion signal 0020h 15 intcmp comparator signal 0022h notes 1. the default priority regulates which maskable interrupt is higher, when two or more maskable interrupts are requested simultaneously. zero signifies the highest priority, while 15 is the lowest. 2. basic configuration types (a), (b), and (c) correspond to (a), (b), and (c) in figure 6-1, respectively. vector basic table configuration address type note 2
81 m pd789415, 789416, 789417 figure 6-1. basic configuration of interrupt functions (a) internal nonmaskable interrupt internal bus interrupt request vector table address generation circuit standby release signal (b) internal maskable interrupt internal bus mk if interrupt request ie vector table address generation circuit standby release signal (c) external maskable interrupt internal bus external interrupt mode register (intm) mk if ie vector table address generation circuit standby release signal edge detection circuit interrupt request if : interrupt request flag ie : interrupt enable flag mk : interrupt mask flag
82 m pd789415, 789416, 789417 6.3 interrupt function control registers the interrupt functions are controlled by the following registers. ? interrupt request flag registers (if0 and if1) ? interrupt mask flag registers (mk0 and mk1) ? external interrupt mode registers (intm0 and intm1) ? program status word (psw) ? key return mode register (krm) table 6-2 lists interrupt requests, the corresponding interrupt request flags, and interrupt mask flags. table 6-2. interrupt request signals and corresponding flags interrupt request signal interrupt request flag interrupt mask flag intwdt intp0 intp1 intp2 intp3 intsr/intcsi0 intst intwt intwti inttm0 inttm1 inttm2 inttm5 intkr intad intcmp tmif4 pif0 pif1 pif2 pif3 srif stif wtif wtifi tmif0 tmif1 tmif2 tmif5 krif adif cmpif tmmk4 pmk0 pmk1 pmk2 pmk3 srmk stmk wtmk wtmki tmmk0 tmmk1 tmmk2 tmmk5 krmk admk cmpmk
83 m pd789415, 789416, 789417 (1) interrupt request flag registers (if0 and if1) an interrupt request flag is set (1), when the corresponding interrupt request is issued, or when the related instruction is executed. it is cleared (0), when the interrupt request is accepted, when a reset signal is input, or when a related instruction is executed. if0 and if1 are set using a 1-bit or 8-bit memory manipulation instruction. a reset input clears if0 and if1 to 00h. figure 6-2. interrupt request flag register format wtif stif srif pif3 pif2 pif1 pif0 tmif4 if0 symbol address when reset r/w ffe0h 00h r/w xxifx 0 1 interrupt request flag no interrupt request signal has been issued. an interrupt request signal has been issued; an interrupt request has been made. cmpif adif krif tmif5 tmif2 tmif1 tmif0 wtifi if1 ffe1h 00h r/w 6 7 543210 6 7 543210 cautions 1. the tmif4 flag can be read- and write-accessed only when the watchdog timer is being used as an interval timer. it must be cleared to 0 if the watchdog timer is used in watchdog timer mode 1 or 2. 2. when port 2 is being used as an output port, and its output level is changed, an interrupt request flag is set, because this port is also used as an external interrupt input. to use port 2 in output mode, therefore, the interrupt mask flag must be set to 1 in advance .
84 m pd789415, 789416, 789417 (2) interrupt mask flag registers (mk0 and mk1) the interrupt mask flags are used to enable and disable the corresponding maskable interrupts. mk0 and mk1 are set using a 1-bit or 8-bit memory manipulation instruction. a reset input loads ffh into mk0 and mk1. figure 6-3. interrupt mask flag register format wtmk stmk srmk pmk3 pmk2 pmk1 pmk0 tmmk4 mk0 xxmkx 0 1 cmpmk admk krmk tmmk5 tmmk2 tmmk1 tmmk0 wtmki mk1 symbol address when reset r/w ffe4h ffh r/w interrupt handling control enable interrupt handling. disable interrupt handling. ffe5h ffh r/w 6 7 543210 6 7 543210 cautions 1. when the watchdog timer is being used in watchdog timer mode 1 or 2, any attempt to read tmmk4 flag results in an undefined value being detected. 2. when port 2 is being used as an output port, and its output level is changed, an interrupt request flag is set, because this port is also used as an external interrupt input. to use port 2 in output mode, therefore, the interrupt mask flag must be set to 1 in advance.
85 m pd789415, 789416, 789417 (3) external interrupt mode register 0 (intm0) intm0 is used to specify an effective edge for intp0 to intp2. intm0 is set using an 8-bit memory manipulation instruction. a reset input clears intm0 to 00h. figure 6-4. external interrupt mode register 0 format es21 es20 es11 es10 es01 es00 0 0 intm0 76543210 es11 0 0 1 1 intp1 effective edge selection es10 0 1 0 1 falling edge rising edge not to be specified both rising and falling edges es21 0 0 1 1 intp2 effective edge selection es20 0 1 0 1 falling edge rising edge not to be specified both rising and falling edges es01 0 0 1 1 intp0 effective edge selection es00 0 1 0 1 falling edge rising edge not to be specified both rising and falling edges symbol address when reset r/w ffech 00h r/w cautions 1. bits 0 and 1 must be fixed to 0. 2. before setting intm0, set the corresponding interrupt mask flag register to 1 to disable interrupts. to enable interrupts, clear (0) the corresponding interrupt request flag, then the corresponding interrupt mask flag register.
86 m pd789415, 789416, 789417 (4) external interrupt mode register 1 (intm1) intm1 is used to specify an effective edge for intp3 and intcmp. intm1 is set using an 8-bit memory manipulation instruction. a reset input clears intm1 to 00h. figure 6-5. external interrupt mode register 1 format es61 es60 0000 es31 es30 intm1 76543210 es31 0 0 1 1 intp3 effective edge selection e30 0 1 0 1 falling edge rising edge not to be specified both rising and falling edges es61 0 0 1 1 intcmp effective edge selection es60 0 1 0 1 falling edge rising edge not to be specified both rising and falling edges symbol address when reset r/w ffedh 00h r/w cautions 1. bits 2 to 5 must be fixed to 0. 2. before setting intm1, set the corresponding interrupt mask flag register to 1 to disable interrupts. to enable interrupts, clear (0) the corresponding interrupt request flag, then the corresponding interrupt mask flag register.
87 m pd789415, 789416, 789417 (5) program status word (psw) the program status word is used to hold the instruction execution result and the current status of the interrupt requests. the ie flag, used to enable and disable maskable interrupts, is mapped to the psw. the psw can be read- and write-accessed in 8-bit units, as well as in 1-bit units when using bit manipulation instructions and dedicated instructions (ei and di). when a vector interrupt is accepted, the psw is automatically saved to a stack, and the ie flag is reset (0). an reset input loads 02h into the psw. figure 6-6. program status word configuration ie z 0 ac 0 0 1 cy psw symbol when reset 02h 76543210 ie 0 1 disable enable whether to enable/disable interrupt acceptance used in the execution of ordinary instructions (6) key return mode register (krm) the krm is used to specify the pin at which a key return signal is detected. the krm is set using a 1-bit or 8-bit memory manipulation instruction. bit 0 (krm0) is set in 4-bit units for the kr0/p40 to kr3/p43 pins. bits 4 and 5 (krm4 and krm5) are set in 1-bit units for the kr4/p44 and kr5/p45 pins, respectively. a reset input clears the krm to 00h. figure 6-7. key return mode register format krmn 0 1 key return signal detection selection undetected detected (at the falling edge of port 4) 0 0 krm5 krm4 0 0 0 krm0 krm symbol address when reset r/w fff5h 00h r/w 76543210 cautions 1. bits 1, 2, 3, 6, and 7 must be fixed to 0. 2. when krm is set (1), the corresponding output pin is connected to a pull-up resistor unless it is in output mode. in output mode, the pull-up resistor is not connected. 3. before setting the krm, set bit 5 of mk1 (krmk = 1) to disable interrupts. to enable interrupts, clear bit 5 of if1 (krif = 0), then bit 5 of mk1 (krmk = 0).
88 m pd789415, 789416, 789417 figure 6-8. falling edge detection circuit p40/kr0 p41/kr1 p42/kr2 p43/kr3 p44/kr4 p45/kr5 falling edge detection circuit krmk krif set signal standby release signal key return mode register (krm) note selector note selector used to select the pin to be used for falling edge input
89 m pd789415, 789416, 789417 7. standby function 7.1 standby function the standby function is supported to minimize the systems power consumption. there are two standby modes: halt and stop. halt and stop modes are selected using the halt and stop instructions, respectively. (1) halt mode in halt mode, the cpu clock is stopped. interleaving normal mode with halt mode can reduce the average power consumption. (2) stop mode in stop mode, the main system clock is stopped. as a result, main system clock-based operation is also stopped, thus minimizing power consumption. caution before shifting to stop mode, first stop the operation of the hardware, then execute the stop instruction.
90 m pd789415, 789416, 789417 table 7-1. operation statuses in halt mode halt mode operation status while the main system clock is running halt mode operation status while the subsystem clock is running while the subsystem clock is running while the subsystem clock is not running while the main system clock is running while the main system clock is not running clock generator can operate with the main system clock. does not run. cpu does not run. port (output latch) remains in the state existing before the selection of halt mode. 16-bit timer counter (tm5) operation enabled does not run. 8-bit timer/event counter (tm0 and tm1) operation enabled operation enabled note 1 8-bit timer counter (tm2) operation enabled operation enabled note 2 operation enabled operation enabled note 3 clock timer operation enabled operation enabled note 2 operation enabled operation enabled note 3 watchdog timer operation enabled operation disabled serial interface operation enabled operation enabled note 4 a/d converter operation disabled lcd controller/driver operation enabled operation enabled note 2 operation enabled operation enabled note 3 comparator operation enabled note 5 external interrupt operation enabled note 6 notes 1. operation is enabled only when ti0 or ti1 is selected as the count clock. 2. operation is enabled while the main system clock is selected. 3. operation is enabled while the subsystem clock is selected. 4. operation is enabled in both three-wire serial i/o and uart modes while an external clock is being used. 5. operation is enabled while tm2 is operating, or as an external interrupt. 6. maskable interrupt that is not masked item
91 m pd789415, 789416, 789417 table 7-2. operation statuses in stop mode stop mode operation status while the main system clock is running while the subsystem clock is running while the subsystem clock is not running clock generator does not operate with the main system clock. cpu does not run. port (output latch) remains in the state existing before the selection of stop mode. 16-bit timer counter (tm5) does not run. 8-bit timer/event counter (tm0 and tm1) operation enabled note 1 8-bit timer counter (tm2) operation enabled note 2 does not run. clock timer operation enabled note 2 does not run. watchdog timer does not run. serial interface operation enabled note 3 a/d converter does not run. lcd controller/driver operation enabled note 2 does not run. comparator operation enabled notes 5 and 6 operation enabled note 6 external interrupt operation enabled note 4 notes 1. operation is enabled only when ti0 or ti1 is selected as the count clock. 2. operation is enabled while the subsystem clock is selected. 3. operation is enabled in both three-wire serial i/o and uart modes while an external clock is being used. 4. maskable interrupt that is not masked 5. operation is enabled while tm2 is running. 6. operation is enabled as an external interrupt. item
92 m pd789415, 789416, 789417 7.2 standby function control register the oscillation settling time selection register (osts) is used to control the wait time, from the time the stop mode is deselected by an interrupt request, until oscillation settles. the osts is manipulated using an 8-bit memory manipulation instruction. a reset input loads 04h into the osts. if a reset input is used to deselect stop mode, the time required for oscillation to settle will be 2 15 /f x , rather than 2 17 /f x . figure 7-1. oscillation settling time selection register format osts2 osts1 osts0 osts symbol address when reset r/w fffah 04h r/w 76543210 oscillation settling time selection osts2 0 0 1 osts1 0 1 0 0000 osts0 0 0 0 2 12 /fx 2 15 /fx 2 17 /fx not to be set (819 s) (6.55 ms) (26.2 ms) m other settings 0 caution the wait time required to deselect stop mode does not include the time (a in the following chart) required for the clock oscillation to settle after stop mode is deselected, regardless of whether stop mode is deselected by a reset input or interrupt. stop mode release x1 pin voltage waveform v ss a remarks 1. f x : main system clock oscillation frequency 2. the parenthesized values apply to operation at f x = 5.0 mhz.
93 m pd789415, 789416, 789417 8. reset functions the m pd789415, m pd789416, and m pd789417 can be reset using the following signals. (1) external reset signal input to the reset pin (2) internal reset signal generated upon the elapse of the period set in the watchdog timer, used for detecting an unintended program loop the external and internal reset signals are functionally equivalent. when reset is input, they cause program execution to begin at the addresses indicated at addresses 0000h and 0001h, respectively. if a low level signal is applied to the reset pin, or if the watchdog timer overflows, a reset occurs, causing each piece of the hardware to enter the states listed in table 8-1. while a reset signal is being input, or while the oscillation frequency is settling immediately after the end of a reset sequence, each pin remains in the high- impedance state. if a high level signal is applied to the reset pin, a reset sequence is terminated, and program execution begins once the oscillation settling time (2 15 /f x ) elapses. a watchdog timer overflow-based reset sequence is terminated automatically. similarly, program execution begins upon the elapse of the oscillation settling time (2 15 /f x ). cautions 1. to use an external reset sequence, supply a low level signal to the reset pin and maintain the signal for at least 10 m s. 2. when a reset is used to deselect stop mode, the information related to the stop mode is held during the reset sequence, that is, while the reset signal is applied. the port pins remain in the high-impedance state, however. figure 8-1. reset function block diagram reset count clock reset control circuit watchdog timer stop over- flow reset signal interrupt function
94 m pd789415, 789416, 789417 table 8-1. state of the hardware after a reset hardware state after reset program counter (pc) note 1 loaded with the contents of the reset vector table (0000h, 0001h) stack pointer (sp) undefined program status word (psw) 02h ram data memory undefined note 2 general-purpose register undefined note 2 ports (p0, p2, p4, p5, p8, p9) (output latch) 00h port mode registers (pm0, pm2, pm4, pm5, pm8, pm9) ffh pull-up resistor option registers (pu0 to pu2) 00h processor clock control register (pcc) 02h subsystem clock oscillation mode register (sckm) 00h subclock control register (css) 00h oscillation settling time selection register (osts) 04h 16-bit timer/counter 5 timer register (tm5) 0000h compare register (cr50) ffffh capture register (tcp5) undefined mode control register (tmc5) 00h 8-bit timer/event counters 0 to 2 timer registers (tm0 to tm2) 00h compare registers (cr00 to cr20) undefined mode control registers (tmc0 to tmc2) 00h clock timer mode control register (wtm) 00h watchdog timer timer clock selection register (tcl2) 00h mode register (wdtm) 00h a/d converter mode register (adm) 00h a/d converter input selection register (ads) 00h 10-bit a/d conversion result register (adcr) undefined comparator mode register 0 (cmprm0) 00h lcd controller/driver lcd display mode register (lcdm) 00h lcd port selector (lps) 00h lcd clock control register (lcdc) 00h serial interface mode register (csim0) 00h asynchronous serial interface mode register (asim) 00h asynchronous serial interface status register (asis) 00h baud rate generator control register (brgc) 00h transmission shift register (txs) ffh reception buffer register (rxb) undefined interrupts request flag registers (if0, if1) 00h mask flag registers (mk0, mk1) ffh external interrupt mode registers (intm0, intm1) 00h key return mode register (krm) 00h notes 1. while a reset signal is being input, and during the oscillation settling period, the contents of the pc will be undefined, while the remainder of the hardware will be the same as after the reset. 2. in standby mode, the ram enters the hold state after a reset.
95 m pd789415, 789416, 789417 9. mask options the m pd789415, m pd789416, and m pd789417 have the following mask options. ? mask option for p50 to p53 this option is used to specify whether to incorporate a pull-up resistor, as follows: <1> to indicate whether a pull-up resistor is to be incorporated, an individual bit is specified, independently of the other bits. <2> the specification of each bit indicates that a pull-up resistor is not to be incorporated. ? mask option for the v lc0 to v lc2 pins and bias pin this option is used to specify whether a voltage division resistor is to be incorporated for the lcd driver, as listed below: r lc1 (2 r lc2 ) none 20 k w 200 k w r lc2 none -- 10 k w - 100 k w - : selectable - : not selectable lips lips: bit 4 of the lcd display mode register (lcdm) p-ch v dd0 v lc0 v lc1 v lcd v lc2 v ss0 r lc2 r lc2 r lc2 r lc1 bias
96 m pd789415, 789416, 789417 10. instruction set overview the instruction set for the m pd789415, m pd789416, and m pd789417 is listed later. 10.1 legend 10.1.1 operand formats and descriptions the description made in the operand field of each instruction conforms to the operand format for the instructions listed below (the details conform with the assembly specification). if more than one operand format is listed for an instruction, one is selected. uppercase letters, #, !, $, and a pair of [ and ] are used to specify keywords, which must be written exactly as they appear. the meanings of these special characters are as follows: ? #: immediate data specification ? $: relative address specification ? !: absolute address specification ? [ and ]: indirect address specification immediate data should be described using appropriate values or labels. the specification of values and labels must be accompanied by #, !, $, or a pair of [ and ]. operand registers, expressed as r or rp in the formats, can be described using both functional names (x, a, c, etc.) and absolute names (r0, r1, r2, and other names listed in table 10-1). table 10-1. operand formats and descriptions format description r rp sfr x (r0), a (r1), c (r2), b (r3), e (r4), d (r5), l (r6), h (r7) ax (rp0), bc (rp1), de (rp2), hl (rp3) special function register symbol saddr saddrp fe20h to ff1fh: immediate data or label fe20h to ff1fh: immediate data or label (even addresses only) addr16 addr5 0000h to ffffh: immediate data or label (only even address for 16-bit data transfer instructions) 0040h to 007fh: immediate data or label (even addresses only) word byte bit 16-bit immediate data or label 8-bit immediate data or label 3-bit immediate data or label remark for the special function register symbols, see table 4-1 .
97 m pd789415, 789416, 789417 10.1.2 descriptions of the operation field a : a register (8-bit accumulator) x : x register b : b register c : c register d : d register e : e register h : h register l : l register ax : ax register pair (16-bit accumulator) bc : bc register pair de : de register pair hl : hl register pair pc : program counter sp : stack pointer psw : program status word cy : carry flag ac : auxiliary carry flag z : zero flag ie : interrupt request enable flag nmis : flag to indicate that a nonmaskable interrupt is being handled () : contents of a memory location indicated by a parenthesized address or register name x h , x l : upper and lower 8 bits of a 16-bit register ^ : logical product (and) : logical sum (or) : exclusive or ? : inverted data addr16 : 16-bit immediate data or label jdisp8 : signed 8-bit data (displacement value) 10.1.3 description of the flag operation field (blank) : no change 0 : to be cleared to 0 1 : to be set to 1 : to be set or cleared according to the result r : to be restored to the previous value
98 m pd789415, 789416, 789417 10.2 operations flag zaccy mov r, #byte 3 6 r ? byte saddr, #byte 3 6 (saddr) ? byte sfr, #byte 3 6 sfr ? byte a, r note 1 24a ? r r, a note 1 24r ? a a, saddr 2 4 a ? (saddr) saddr, a 2 4 (saddr) ? a a, sfr 2 4 a ? sfr sfr, a 2 4 sfr ? a a, !addr16 3 8 a ? (addr16) !addr16, a 3 8 (addr16) ? a psw, #byte 3 6 psw ? byte a, psw 2 4 a ? psw psw, a 2 4 psw ? a a, [de] 1 6 a ? (de) [de], a 1 6 (de) ? a a, [hl] 1 6 a ? (hl) [hl], a 1 6 (hl) ? a a, [hl + byte] 2 6 a ? (hl + byte) [hl + byte], a 2 6 (hl + byte) ? a xch a, x 1 4 a ? x a, r note 2 26a ? r a, saddr 2 6 a ? (saddr) a, sfr 2 6 a ? (sfr) a, [de] 1 8 a ? (de) a, [hl] 1 8 a ? (hl) a, [hl + byte] 2 8 a ? (hl + byte) movw rp, #word 3 6 rp ? word ax, saddrp 2 6 ax ? (saddrp) saddrp, ax 2 8 (saddrp) ? ax ax, rp note 3 1 4 ax ? rp rp, ax note 3 1 4 rp ? ax notes 1. except when r = a. 2. except when r = a or x. 3. only when rp = bc, de, or hl. remark the instruction clock cycle is based on the cpu clock (f cpu ), specified in the processor clock controller register (pcc). operation clock byte operand mnemonic
99 m pd789415, 789416, 789417 flag zaccy xchw ax, rp note 3 1 8 ax ? rp add a, #byte 2 4 a, cy ? a + byte saddr, #byte 3 6 (saddr), cy ? (saddr) + byte a, r 2 4 a, cy ? a + r a, saddr 2 4 a, cy ? a + (saddr) a, !addr16 3 8 a, cy ? a + (addr16) a, [hl] 1 6 a, cy ? a + (hl) a, [hl + byte] 2 6 a, cy ? a + (hl + byte) addc a, #byte 2 4 a, cy ? a + byte + cy saddr, #byte 3 6 (saddr), cy ? (saddr) + byte + cy a, r 2 4 a, cy ? a + r + cy a, saddr 2 4 a, cy ? a + (saddr) + cy a, !addr16 3 8 a, cy ? a + (addr16) + cy a, [hl] 1 6 a, cy ? a + (hl) + cy a, [hl + byte] 2 6 a, cy ? a + (hl + byte) + cy sub a, #byte 2 4 a, cy ? a - byte saddr, #byte 3 6 (saddr), cy ? (saddr) - byte a, r 2 4 a, cy ? a - r a, saddr 2 4 a, cy ? a - (saddr) a, !addr16 3 8 a, cy ? a - (addr16) a, [hl] 1 6 a, cy ? a - (hl) a, [hl + byte] 2 6 a, cy ? a - (hl + byte) subc a, #byte 2 4 a, cy ? a - byte - cy saddr, #byte 3 6 (saddr), cy ? (saddr) - byte - cy a, r 2 4 a, cy ? a - r - cy a, saddr 2 4 a, cy ? a - (saddr) - cy a, !addr16 3 8 a, cy ? a - (addr16) - cy a, [hl] 1 6 a, cy ? a - (hl) - cy a, [hl + byte] 2 6 a, cy ? a - (hl + byte) - cy and a, #byte 2 4 a ? a byte saddr, #byte 3 6 (saddr) ? (saddr) byte a, r 2 4 a ? a r a, saddr 2 4 a ? a (saddr) a, !addr16 3 8 a ? a (addr16) a, [hl] 1 6 a ? a (hl) a, [hl + byte] 2 6 a ? a (hl + byte) remark the instruction clock cycle is based on the cpu clock (f cpu ), specified in the processor clock controller register (pcc). operation clock byte operand mnemonic
100 m pd789415, 789416, 789417 flag zaccy or a, #byte 2 4 a, ? a byte saddr, #byte 3 6 (saddr) ? (saddr) byte a, r 2 4 a ? a r a, saddr 2 4 a ? a (saddr) a, !addr16 3 8 a ? a (addr16) a, [hl] 1 6 a ? a (hl) a, [hl + byte] 2 6 a ? a (hl + byte) xor a, #byte 2 4 a ? a byte saddr, #byte 3 6 (saddr) ? (saddr) byte a, r 2 4 a ? a r a, saddr 2 4 a ? a (saddr) a, !addr16 3 8 a ? a (addr16) a, [hl] 1 6 a ? a (hl) a, [hl + byte] 2 6 a ? a (hl + byte) cmp a, #byte 2 4 a - byte saddr, #byte 3 6 (saddr) - byte a, r 2 4 a - r a, saddr 2 4 a - (saddr) a, !addr16 3 8 a - (addr16) a, [hl] 1 6 a - (hl) a, [hl + byte] 2 6 a - (hl + byte) addw ax, #word 3 6 ax, cy ? ax + word subw ax, #word 3 6 ax, cy ? ax - word cmpw ax, #word 3 6 ax - word inc r 2 4 r ? r + 1 saddr 2 4 (saddr) ? (saddr) + 1 dec r 2 4 r ? r - 1 saddr 2 4 (saddr) ? (saddr) - 1 incw rp 1 4 rp ? rp + 1 decw rp 1 4 rp ? rp - 1 ror a, 1 1 2 (cy, a 7 ? a 0 , a m - 1 ? a m ) 1 rol a, 1 1 2 (cy, a 0 ? a 7 , a m+1 ? a m ) 1 rorc a, 1 1 2 (cy ? a 0 , a 7 ? cy, a m - 1 ? a m ) 1 rolc a, 1 1 2 (cy ? a 7 , a 0 ? cy, a m+1 ? a m ) 1 remark the instruction clock cycle is based on the cpu clock (f cpu ), specified in the processor clock controller register (pcc). operation clock byte operand mnemonic
101 m pd789415, 789416, 789417 flag zaccy set1 saddr. bit 3 6 (saddr. bit) ? 1 sfr. bit 3 6 sfr. bit ? 1 a. bit 2 4 a. bit ? 1 psw. bit 3 6 psw. bit ? 1 [hl]. bit 2 10 (hl). bit ? 1 clr1 saddr. bit 3 6 (saddr. bit) ? 0 sfr. bit 3 6 sfr. bit ? 0 a. bit 2 4 a. bit ? 0 psw. bit 3 6 psw. bit ? 0 [hl]. bit 2 10 (hl). bit ? 0 set1 cy 1 2 cy ? 11 clr1 cy 1 2 cy ? 00 not1 cy 1 2 cy ? cy call !addr16 3 6 (sp - 1) ? (pc + 3) h , (sp - 2) ? (pc + 3) l , pc ? addr16, sp ? sp - 2 callt [addr5] 1 8 (sp - 1) ? (pc + 1) h , (sp - 2) ? (pc + 1) l , pc h ? (00000000, addr5 + 1), pc l ? (00000000, addr5), sp ? sp - 2 ret 1 6 pc h ? (sp + 1), pc l ? (sp), sp ? sp + 2 reti 1 8 pc h ? (sp + 1), pc l ? (sp), psw ? (sp + 2), sp ? sp + 3, nmis ? 0 rrr push psw 1 2 (sp - 1) ? psw, sp ? sp - 1 rp 1 4 (sp - 1) ? rp h , (sp - 2) ? rp l , sp ? sp - 2 pop psw 1 4 psw ? (sp), sp ? sp + 1 r r r rp 1 6 rp h ? (sp + 1), rp l ? (sp), sp ? sp + 2 movw sp, ax 2 8 sp ? ax ax, sp 2 6 ax ? sp br !addr16 3 6 pc ? addr16 $addr16 2 6 pc ? pc + 2 + jdisp8 ax 1 6 pc h ? a, pc l ? x remark the instruction clock cycle is based on the cpu clock (f cpu ), specified in the processor clock controller register (pcc). operation clock byte operand mnemonic
102 m pd789415, 789416, 789417 flag zaccy bc $addr16 2 6 pc ? pc + 2 + jdisp8 if cy = 1 bnc $addr16 2 6 pc ? pc + 2 + jdisp8 if cy = 0 bz $addr16 2 6 pc ? pc + 2 + jdisp8 if z = 1 bnz $addr16 2 6 pc ? pc + 2 + jdisp8 if z = 0 bt saddr. bit, $addr16 4 10 pc ? pc + 4 + jdisp8 if (saddr. bit) = 1 sfr. bit, $addr16 4 10 pc ? pc + 4 + jdisp8 if sfr. bit = 1 a. bit, $addr16 3 8 pc ? pc + 3 + jdisp8 if a. bit = 1 psw. bit, $addr16 4 10 pc ? pc + 4 + jdisp8 if psw. bit = 1 bf saddr. bit, $addr16 4 10 pc ? pc + 4 + jdisp8 if (saddr. bit) = 0 sfr. bit, $addr16 4 10 pc ? pc + 4 + jdisp8 if sfr. bit = 0 a. bit, $addr16 3 8 pc ? pc + 3 + jdisp8 if a. bit = 0 psw. bit, $addr16 4 10 pc ? pc + 4 + jdisp8 if psw. bit = 0 dbnz b, $addr16 2 6 b ? b - 1, then pc ? pc + 2 + jdisp8 if b 1 0 c, $addr16 2 6 c ? c - 1, then pc ? pc + 2 + jdisp8 if c 1 0 saddr, $addr16 3 8 (saddr) ? (saddr) - 1, then pc ? pc + 3 + jdisp8 if (saddr) 1 0 nop 1 2 no operation ei 3 6 ie ? 1 (enable interrupt) di 3 6 ie ? 0 (disable interrupt) halt 1 2 set halt mode stop 1 2 set stop mode remark the instruction clock cycle is based on the cpu clock (f cpu ), specified in the processor clock controller register (pcc). operation clock byte operand mnemonic
103 m pd789415, 789416, 789417 11. electrical characteristics (target values) caution the ratings listed below are target values for the product, established in the development stage. when designing an application system, refer to the following data sheet, which details the formal electrical characteristics: m pd789415, 789416, 789417 data sheet: in preparation absolute maximum ratings (t a = 25 c) (target values) parameter symbol conditions rated value unit supply voltage v dd - 0.3 to +7.0 v input voltage v i1 pins other than those for port 5 - 0.3 to v dd + 0.3 v v i2 p50-p53 n-channel, open-drain - 0.3 to +13 v output voltage v o - 0.3 to v dd + 0.3 v output high current i oh each pin peak value - 10 ma rms - 5ma total for all pins peak value - 30 ma rms - 15 ma output low current i ol note each pin peak value 30 ma rms 15 ma total for all pins peak value 160 ma rms 80 ma operating ambient temperature t a - 40 to +85 c storage temperature t stg - 65 to +150 c note calculate rms with [rms] = [peak value] ? duty cycle. caution absolute maximum ratings are rated values beyond which physical damage w ill be caused to the product; if the rated value of any of the parameters in the above table is exceeded, even momentarily, the quality of the product may deteriorate. always use the product within its rated values. remark the characteristic of a dual-function pin does not differ between the port function and the secondary function, unless otherwise stated.
104 m pd789415, 789416, 789417 characteristics of the main system clock oscillation circuit (t a = - 40 to +85 c, v dd = 1.8 to 5.5 v) (target values) resonator recommended circuit parameter conditions min. typ. max. unit ceramic resonator oscillator frequency (f x ) note 1 v dd = oscillation voltage range 1.0 5.0 mhz oscillation settling time note 2 after v dd reaches min. of the oscillation voltage range 4ms crystal oscillator frequency (f x ) note 1 1.0 5.0 mhz oscillation settling time note 2 v dd = 4.5 to 5.5 v 10 ms 30 external clock x1 input frequency (f x ) note 1 1.0 5.0 mhz x1 input high/low level width (t xh , t xl ) 100 500 ns notes 1. only the characteristic of the oscillation circuit is indicated. see the description of the ac characteristic for the instruction execution time. 2. time required for oscillation to settle once a reset sequence ends or stop mode is deselected. cautions 1. when using the main system clock osc illation circuit, observe the following c onditions for the wiring of that section enclosed in dotted lines in the above diagrams, so as to avoid the influence of the wiring capacitance. ? keep the wiring as short as possible. ? do not allow signal wires to cross one another. ? keep the wiring away from wires that carry a high, non-stable current. ? keep the grounding point of the capacitors at the same level as v ss . ? do not connect the grounding point to a grounding wire that carries a high current. ? do not extract a signal from the oscillation circuit. 2. before switching from the subsystem clock back to the main system clock, always allow sufficient time for the oscillation to settle by specifying it in the program. x1 x2 ic c1 c2 x1 x2 ic c1 c2 r1 x1 x2 pd74hcu04 m
105 m pd789415, 789416, 789417 xt1 xt2 pd74hcu04 m characteristics of the main system clock oscillation circuit (t a = - 40 to +85 c, v dd = 1.8 to 5.5 v) (target values) resonator recommended circuit parameter conditions min. typ. max. unit crystal oscillator frequency (f xt ) note 1 32 32.768 35 khz oscillation settling time note 2 v dd = 4.5 to 5.5 v 1.2 2 s 10 external clock xt1 input frequency (f xt ) note 1 32 35 khz xt1 input high/low level width (t xth , t xtl ) 14.3 15.6 m s notes 1. only the characteristic of the oscillation circuit is indicated. see the description of the ac characteristic for the instruction execution time. 2. time required for oscillation to settle after v dd reaches the min. value of the oscillation voltage range. cautions 1. when using the subsystem clock osc illation circuit, observe the following c onditions for the wiring of that section enclosed in dotted lines in the above diagrams, so as to avoid the influence of the wiring capacitance. ? keep the wiring as short as possible. ? do not allow signal wires to cross one another. ? keep the wiring away from wires that carry a high, non-stable current. ? keep the grounding point of the capacitors at the same level as v ss . ? do not connect the grounding point to a grounding wire that carries a high current. ? do not extract a signal from the oscillation circuit. 2. the subsystem clock osc illation circuit is designed to h ave a low amplification degree so as to maintain a low current drain. therefore, it is more likely to malfunction as a result of noise than the main system clock osc illation circuit. when using the sub system clock, therefore, pay particularly careful attention to how it is wired. xt1 xt2 ic c3 c4 r2
106 m pd789415, 789416, 789417 dc characteristics (t a = - 40 to +85 c, v dd = 1.8 to 5.5 v) (target values) parameter symbol conditions min. typ. max. unit v ih1 p00-p03, p46, p47, p60- v dd = 2.7 to 5.5 v 0.7v dd v dd v p66, p80-p87, p90-p93 0.9v dd v dd v v ih2 p50-p53 v dd = 2.7 to 5.5 v 0.7v dd 12 v 0.9v dd 12 v v ih3 v dd = 2.7 to 5.5 v 0.8v dd v dd v 0.9v dd v dd v v ih4 x1, x2 v dd - 0.1 v dd v v il1 p00-p03, p46, p47, p60- v dd = 2.7 to 5.5 v 0 0.3v dd v p66, p80-p87, p90-p93 0 0.1v dd v v il2 p50-p53 v dd = 2.7 to 5.5 v 0 0.3v dd v 0 0.1v dd v v il3 2.7 v v dd 5.5 v 0 0.2v dd v 0 0.1v dd v v il4 x1, x2 0 0.1 v v oh v dd = 4.5 to 5.5 v, i oh = - 1 ma v dd - 1.0 v v dd = 4.5 to 5.5 v, i oh = - 100 m av dd - 0.5 v v ol1 pins other than those for port 5 v dd = 4.5 to 5.5 v, i ol = 10 ma 1.0 v v dd = 4.5 to 5.5 v, i ol = 400 m a 0.5 v v ol2 p50-p53 v dd = 4.5 to 5.5 v, i ol = 10 ma 1.0 v v dd = 4.5 to 5.5 v, i ol = 1.6 ma 0.4 v l lih1 v in = v dd pins other than the x1 pin, x2 pin, or those for port 5 3 m a l lih2 x1, x2 20 m a l lih3 v in = 12 v p50-p53 (n-channel, open-drain) 20 m a l lil1 v in = 0 v pins other than the x1 pin, x2 pin, or those for port 5 - 3 m a l lil2 x1, x2 - 20 m a l lil3 p50-p53 (n-channel, open-drain) during input instruction execution - 30 m a high-level output leakage current i loh v out = v dd 3 m a low-level output leakage current i lol v out = 0 v - 3 m a remark the characteristic of a dual-function pin does not differ between the port function and the secondary function, unless otherwise stated. high-level input voltage low-level input voltage high-level output voltage low-level output voltage high-level input leakage current low-level input leakage current reset, p20-p27, p40-p45 reset, p20-p27, p40-p45
107 m pd789415, 789416, 789417 dc characteristics (t a = - 40 to +85 c, v dd = 1.8 to 5.5 v) (target values) parameter symbol conditions min. typ. max. unit software-specified pull-up resistor r 1 v in = 0 v, for pins other than those for ports 5 and 6 50 100 200 k w mask option- specified pull-up resistor r 2 v in = 0 v, p50-p53 15 30 60 k w i dd1 v dd = 5.0 v 10 % note 3 5.5 16.5 ma v dd = 3.0 v 10 % note 4 0.7 2.1 ma v dd = 2.0 v 10 % note 4 0.4 1.2 ma i dd2 v dd = 5.0 v 10 % 1.2 3.6 ma v dd = 3.0 v 10 % 0.5 1.5 ma v dd = 2.0 v 10 % 0.3 0.9 ma i dd3 v dd = 5.0 v 10 % 100 200 m a v dd = 3.0 v 10 % 70 140 m a v dd = 2.0 v 10 % 50 100 m a i dd4 v dd = 5.0 v 10 % 25 55 m a v dd = 3.0 v 10 % 525 m a v dd = 2.0 v 10 % 2.5 12.5 m a i dd5 v dd = 5.0 v 10 % 0.1 30 m a v dd = 3.0 v 10 % 0.05 10 m a v dd = 2.0 v 10 % 0.05 10 m a i dd6 v dd = 5.0 v 10 % 6.1 18.3 m a v dd = 3.0 v 10 % 1.3 2.9 m a v dd = 2.0 v 10 % 1.0 3.0 ma notes 1. the power supply current does not include av ref , av dd , or the port current (including the current flowing through the built-in pull-up resistor). 2. when the main system clock is not running. 3. during high-speed mode operation (when the processor clock control register (pcc) is cleared to 00h.) 4. during low-speed mode operation (when 02h is loaded into the pcc.) remark the characteristic of a dual-function pin does not differ between the port function and the secondary function, unless otherwise stated. power supply current note 1 5.0-mhz crystal oscillation operating mode 5.0-mhz crystal oscillation halt mode 32.768-khz crystal oscillation operating mode note 2 32.768-khz crystal oscillation halt mode note 2 32.768-khz crystal stop stop mode 5.0-mhz crystal oscillation a/d operating mode
108 m pd789415, 789416, 789417 dc characteristics (t a = - 40 to +85 c, v dd = 1.8 to 5.5 v) lcd characteristics (target values) parameter symbol conditions min. typ. max. unit lcd drive voltage v lcd vaon = 1 1.8 v dd v vaon = 0 note 1 2.7 v dd v r lcd1 50 100 200 k w r lcd2 51020 k w v odc i o = 5 m a0 0.2 v v ods i o = 1 m a0 0.2 v notes 1. for an ordinary mode (vaon = 0), t a = - 10 to +85 c. 2. r lcd1 , r lcd2 , or no-resistor can be selected using the mask option. 3. the voltage deviation is the deviation of the segment or common output voltage from the ideal value (v lcdn , where n = 0, 1, or 2). lcd voltage divider resistor note 2 lcd output voltage deviation note 3 (common) lcd output voltage deviation note 3 (segment) 2.2 v v lcd v dd v lcd2 = v lcd 1/3 note1 v lcd0 = v lcd v lcd1 = v lcd 2/3
109 m pd789415, 789416, 789417 operation based on the main system clock ac characteristics (1) basic operations (t a = - 40 to +85 c, v dd = 1.8 to 5.5 v) (target values) parameter symbol conditions min. typ. max. unit t cy v dd = 2.7 to 5.5 v 0.4 32 m s 1.6 32 m s operation based on the subsystem clock 122 m s t tih ,v dd = 2.7 to 5.5 v 0.1 m s t til 1.8 m s f ti v dd = 2.7 to 5.5 v 0 4 mhz 0 275 khz t inth , intp0-intp3 v dd = 2.7 to 5.5 v 10 m s t intl 20 m s t rsl v dd = 2.7 to 5.5 v 10 m s 20 m s t cy vs v dd (main system clock) supply voltage v dd [v] 123456 0.1 0.4 0.5 1.0 2.0 10 60 cycle time t cy [ s] measurement point m cycle time (minimum instruction execution time) ti0 and ti1 input high/low level width ti0 and ti1 input frequency interrupt input high/low level width reset low level width
110 m pd789415, 789416, 789417 (2) serial interface (t a = - 40 to +85 c, v dd = 1.8 to 5.5 v) (a) serial interface channel 0 (i) three-wire serial i/o mode (sck...internal clock output) (target values) parameter symbol conditions min. typ. max. unit sck cycle time t kcy1 v dd = 2.7 to 5.5 v 800 ns 3 200 ns v dd = 2.7 to 5.5 v t kcy1 /2 - 50 n s t kcy1 /2 - 150 ns t sik1 v dd = 2.7 to 5.5 v 150 ns 500 ns t ksi1 v dd = 2.7 to 5.5 v 400 ns 600 ns t kso1 v dd = 2.7 to 5.5 v 0 250 ns 0 1 000 ns note r and c are the resistance and capacitance of the so output line, respectively. (ii) three-wire serial i/o mode (sck...external clock output) (target values) parameter symbol conditions min. typ. max. unit sck cycle time t kcy2 v dd = 2.7 to 5.5 v 800 ns 3 200 ns v dd = 2.7 to 5.5 v 400 n s 1 600 ns t sik2 v dd = 2.7 to 5.5 v 100 ns 150 ns t ksi2 v dd = 2.7 to 5.5 v 400 ns 600 ns t kso2 v dd = 2.7 to 5.5 v 0 300 ns 0 1 000 ns note r and c are the resistance and capacitance of the so output line, respectively. (iii) uart mode (dedicated baud rate generator output) (target values) parameter symbol conditions min. typ. max. unit transfer rate v dd = 2.7 to 5.5 v 78 125 bps 19 531 bps sck high/low level width si setup time (for sck - ) si hold time (for sck - ) delay from sck to so output sck high/low level width si setup time (for sck - ) si hold time (for sck - ) delay from sck to so output t kh2 , t kl2 t kh1 , t kl1 r = 1 k w , c = 100 pf note r = 1 k w , c = 100 pf note
111 m pd789415, 789416, 789417 (iv) uart mode (external clock input) (target values) parameter symbol conditions min. typ. max. unit asck cycle time t kcy3 v dd = 2.7 to 5.5 v 800 ns 3 200 ns v dd = 2.7 to 5.5 v 400 ns 1 600 ns transfer rate v dd = 2.7 to 5.5 v 39 063 bps 9 766 bps 1 m s asck high/low level width asck rising time, falling time t kh3 , t kl3 t r , t f
112 m pd789415, 789416, 789417 ac timing measurement points (except the x1 and xt1 inputs) 0.8v dd 0.2v dd measurement points 0.8v dd 0.2v dd clock timing 1/f x t xl t xh x1 input v ih4 (min.) v il4 (max.) 1/f xt t xtl t xth xt1 input v ih5 (min.) v il5 (max.) ti timing t tih0 , t tih1 t til0 , t til1 ti0, ti1
113 m pd789415, 789416, 789417 serial transfer timing three-wire serial i/o mode: sck t klm t kcym t khm si input data t ksim t sikm output data t ksom so uart mode (external clock input): asck t r t f t kl3 t kcy3 t kh3
114 m pd789415, 789416, 789417 10-bit a/d converter characteristics (t a = - 40 to +85 c, av dd = v dd = 1.8 to 5.5 v, av ss = v ss = 0 v) (target values) item symbol conditions min. typ. max. unit resolution 10 10 10 bit total error note 2.7 v av dd 5.5 v 4 lsb 1.8 v av dd 2.7 v 6 lsb conversion time t conv 14 m s analog input voltage v ian 0v dd v reference voltage av ref 1.8 v dd v note no quantization error ( 1/2 lsb) is included. comparator characteristics (t a = - 40 to +85 c, v dd = 1.8 to 5.5 v ) (target values) item symbol conditions min. typ. max. unit analog input range v cin v dd = 1.8 to 5.5 v 0 v dd v v cref v dd = 2.7 to 5.5 v 1.1 1.4 1.7 v v dd = 1.8 to 2.7 v 1.1 1.2 1.3 v precision v dd = 1.8 to 5.5 v 100 mv data memory stop mode low supply voltage data hold characteristics (t a = - 40 to +85 c) (target values) item symbol conditions min. typ. max. unit v dddr 1.8 5.5 v t srel 0 m s t wait reset by reset 2 15 /f x ms reset by interrupt note ms note 2 12 /f x , 2 15 /f x , or 2 17 /f x can be selected according to the setting of bits 0 to 2 (osts0 to osts2) of the oscillation settling time selection register. remark f x : main system clock oscillation frequency reference voltage input range data hold supply voltage release signal set time oscillation settling time
115 m pd789415, 789416, 789417 data hold timing (stop mode release by reset) v dd data hold mode stop mode halt mode internal reset operation operating mode t srel t wait stop instruction execution v dddr reset data hold timing (standby release signal: stop mode release by interrupt signal) v dd data hold mode stop mode halt mode operating mode t srel t wait stop instruction execution v dddr standby release signal (interrupt request)
116 m pd789415, 789416, 789417 interrupt input timing intp0-intp3 t intl t inth reset input timing reset t rsl
117 m pd789415, 789416, 789417 12. package dimensions 80 pin plastic qfp (14 14) item millimeters inches note each lead centerline is located within 0.13 mm (0.005 inch) of its true position (t.p.) at maximum material condition. p80gc-65-8bt f 0.825 0.032 b 14.000.20 0.551 +0.009 C0.008 s 1.70 max. 0.067 max. m 0.17 0.007 +0.001 C0.003 +0.03 C0.07 +0.009 C0.008 c 14.000.20 0.551 +0.009 C0.008 a 17.200.20 0.6770.008 g 0.825 0.032 h 0.320.06 0.013 +0.002 C0.003 i 0.13 0.005 j 0.65 (t.p.) 0.026 (t.p.) k 1.600.20 0.0630.008 l 0.800.20 0.031 +0.009 C0.008 n 0.10 0.004 p 1.400.10 0.0550.004 q 0.1250.075 0.0050.003 r3 3 +7 C3 +7 C3 d 17.200.20 0.6770.008 41 60 40 61 21 80 20 1 m s q r k m l a b c d j h i f g p n detail of lead end
118 m pd789415, 789416, 789417 80 pin plastic tqfp (fine pitch) ( 12) item millimeters inches i j 0.5 (t.p.) 0.10 0.004 0.020 (t.p.) a note each lead centerline is located within 0.10 mm (0.004 inch) of its true position (t.p.) at maximum material condition. s a 14.00.2 0.551 +0.009 C0.008 b 12.00.2 0.472 +0.009 C0.008 c 12.00.2 0.472 +0.009 C0.008 d 14.00.2 0.551 +0.009 C0.008 f g 1.25 1.25 0.049 0.049 h 0.22 0.0090.002 p80gk-50-be9-4 s 1.27 max. 0.050 max. k 1.00.2 0.039 +0.009 C0.008 l 0.50.2 0.020 +0.008 C0.009 m 0.145 0.0060.002 n 0.10 0.004 p 1.05 0.041 q 0.050.05 0.0020.002 r 5?5? 5?5? +0.05 C0.04 +0.055 C0.045 b c d j h i g f p n l k m q r detail of lead end m 61 60 41 40 21 20 1 80
119 m pd789415, 789416, 789417 appendix a development tools the following development tools are available for developing systems using the m pd789415, m pd789416, and m pd789417. language processing software ra78k0s notes 1, 2, 3 assembler package common to the 78k/0s series cc78k0s notes 1, 2, 3 c compiler package common to the 78k/0s series df789417 notes 1, 2, 3, 7 device file for the m pd789417 sub-series cc78k0s-l notes 1, 2, 3, 7 c compiler library source file common to the 78k/0s series flash memory write tools flashpro ll note 4 dedicated flash writer (formerly, flashpro) fa-80gc note 4 flash memory write adapter fa-80gk note 4 debugging tools nd-k904 notes 4, 7 in-circuit emulator for the m pd789417 sub-series the nd-k904 incorporates the ns-78k9 screen debugger. if-98d note 4 this is an interface board, required when a pc-9800 series (other than a notebook type) are used as the host machine for the nd-k904. if-pcd note 4 this is an interface board, required when an ibm pc/at or compatible (other than a notebook type) is used as the host machine for the nd-k904. if-card note 4 this is an interface board, required when a pc-9800 notebook, ibm pc/at notebook, or compatible is used as the host machine for the nd-k904. np-80gc note 4 emulator probe for the 80-pin plastic qfp (gc-8bt type) np-80gk note 4 emulator probe for the 80-pin plastic tqfp (gk-be9 type) nj-535 note 4 100/120 vac adapter nj-550w note 4 100-240 vac adapter sm78k0s notes 5, 6 system emulator common to all 78k/0s series units df789417 notes 5, 6, 7 device file for the m pd789417 sub-series
120 m pd789415, 789416, 789417 real-time os mx78k0s notes 1, 2, 7 os for the 78k/0s series notes 1. based on the pc-9800 series (ms-dos ? ) 2. based on the ibm pc/at ? and compatibles (pc dos ? /ibm dos ? /ms-dos) 3. based on the hp9000 series 700 ? (hp-ux ? ), sparcstation ? (sunos ? ), and news ? (news-os ? ) 4. product manufactured by and available from naito densei machida seisakusho co., ltd. (044-822- 3813). 5. based on the pc-9800 series (ms-dos + windows ? ) 6. based on the ibm pc/at and compatibles (pc dos/ibm dos/ms-dos + windows) 7. under development remark the ra78k0s, cc78k0s, and sm78k0s can be used in combination with the df789417.
121 m pd789415, 789416, 789417 appendix b related documents documents related to devices document no. japanese english m pd789415, 789416, 789417 preliminary product information u12302j this manual m pd78f9418 preliminary product information u 12321j to be created m pd789407, 789417 sub-series users manual to be released soon to be created 78k/0 series users manual 78k/0s series - instruction u11047j u11047e 78k/0s series instruction summary sheet to be created - 78k/0s series instruction set to be created - m pd789417 sub-series special function registers to be created - documents related to development tools (users manual) document no. japanese english ra78k0s assembler package operation u11622j u11622e language u11599j u11599e structured assembly language u11623j u11623e cc78k/0s c compiler operation u11816j u11816e language u11817j u11817e sm78k0s system simulator windows base reference u11489j u11489e sm78k series system simulator external parts user open interface specifications u10092j u10092e documents related to software to be incorporated into the product (users manual) document no. japanese english os for 78k/0s series mx78k0s to be created to be created caution the above documents may be revised without notice. use the latest versions when you design application systems. document name document name document name
122 m pd789415, 789416, 789417 other documents document no. japanese english ic package manual c10943x smd surface mount technology manual c10535j c10535e quality grades on nec semiconductor device c11531j c11531e nec semiconductor device reliability/quality control system c10983j c10983e electrostatic discharge (esd) test mem-539 - guide to quality assurance for semiconductor device c11893j mei-1202 guide for products related to micro-computer: other companies u11416j - caution the above documents may be revised without notice. use the latest versions when you design application systems. document name
123 m pd789415, 789416, 789417 notes for cmos devices 1 precaution against esd for semiconductors note: strong electric field, when exposed to a mos device, can cause destruction of the gate oxide and ultimately degrade the device operation. steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred. environmental control must be adequate. when it is dry, humidifier should be used. it is recommended to avoid using insulators that easily build static electricity. semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. all test and measurement tools including work bench and floor should be grounded. the operator should be grounded using wrist strap. semiconductor devices must not be touched with bare hands. similar precautions need to be taken for pw boards with semiconductor devices on it. 2 handling of unused input pins for cmos note: no connection for cmos device inputs can be cause of malfunction. if no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. cmos devices behave differently than bipolar or nmos devices. input levels of cmos devices must be fixed high or low by using a pull-up or pull-down circuitry. each unused pin should be connected to v dd or gnd with a resistor, if it is considered to have a possibility of being an output pin. all handling related to the unused pins must be judged device by device and related specifications governing the devices. 3 status before initialization of mos devices note: power-on does not necessarily define initial status of mos device. production process of mos does not define the initial operation status of the device. immediately after the power source is turned on, the devices with reset function have not yet been initialized. hence, power-on does not guarantee out-pin levels, i/o settings or contents of registers. device is not initialized until the reset signal is received. reset operation must be executed imme- diately after power-on for devices having reset function.
124 m pd789415, 789416, 789417 fip and iebus are trademarks of nec corporation. ms-dos and windows are trademarks or trademark of microsoft corporation in the united states and/or other countries. ibm dos, pc/at, and pc dos are trademarks of ibm corporation. hp9000 series 700 and hp-ux are trademarks of hewlett-packard company. sparcstation is a trademark of sparc international, inc. sunos is a trademark of sun microsystems, inc. news and news-os are trademarks of sony corporation.
125 m pd789415, 789416, 789417 regional information some information contained in this document may vary from country to country. before using any nec product in your application, piease contact the nec office in your country to obtain a list of authorized representatives and distributors. they will verify: ? device availability ? ordering information ? product release schedule ? availability of related technical literature ? development environment specifications (for example, specifications for third-party tools and components, host computers, power plugs, ac supply voltages, and so forth) ? network requirements in addition, trademarks, registered trademarks, export restrictions, and other legal issues may also vary from country to country. nec electronics inc. (u.s.) santa clara, california tel: 800-366-9782 fax: 800-729-9288 nec electronics (germany) gmbh duesseldorf, germany tel: 0211-65 03 02 fax: 0211-65 03 490 nec electronics (uk) ltd. milton keynes, uk tel: 01908-691-133 fax: 01908-670-290 nec electronics italiana s.r.1. milano, italy tel: 02-66 75 41 fax: 02-66 75 42 99 nec electronics (germany) gmbh benelux office eindhoven, the netherlands tel: 040-2445845 fax: 040-2444580 nec electronics (france) s.a. velizy-villacoublay, france tel: 01-30-67 58 00 fax: 01-30-67 58 99 nec electronics (france) s.a. spain office madrid, spain tel: 01-504-2787 fax: 01-504-2860 nec electronics (germany) gmbh scandinavia office taeby, sweden tel: 08-63 80 820 fax: 08-63 80 388 nec electronics hong kong ltd. hong kong tel: 2886-9318 fax: 2886-9022/9044 nec electronics hong kong ltd. seoul branch seoul, korea tel: 02-528-0303 fax: 02-528-4411 nec electronics singapore pte. ltd. united square, singapore 1130 tel: 253-8311 fax: 250-3583 nec electronics taiwan ltd. taipei, taiwan tel: 02-719-2377 fax: 02-719-5951 nec do brasil s.a. sao paulo-sp, brasil tel: 011-889-1680 fax: 011-889-1689 j96. 8
m pd789415, 789416, 789417 the export of this product from japan is regulated by the japanese government. to export this product may be prohibited without governmental license, the need for which must be judged by the customer. the export or re-export of this product from a country other than japan may also be prohibited without a license from that country. please call an nec sales representative. no part of this document may be copied or reproduced in any form or by any means without the prior written consent of nec corporation. nec corporation assumes no responsibility for any errors which may appear in this document. nec corporation does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from use of a device described herein or any other liability arising from use of such device. no license, either express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of nec corporation or others. while nec corporation has been making continuous effort to enhance the reliability of its semiconductor devices, the possibility of defects cannot be eliminated entirely. to minimize risks of damage or injury to persons or property arising from a defect in an nec semiconductor device, customers must incorporate sufficient safety measures in its design, such as redundancy, fire-containment, and anti-failure features. nec devices are classified into the following three quality grades: "standard", "special", and "specific". the specific quality grade applies only to devices developed based on a customer designated "quality assurance program" for a specific application. the recommended applications of a device depend on its quality grade, as indicated below. customers must check the quality grade of each device before using it in a particular application. standard: computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots special: transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support) specific: aircrafts, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems or medical equipment for life support, etc. the quality grade of nec devices is "standard" unless otherwise specified in nec's data sheets or data books. if customers intend to use nec devices for applications other than those specified for standard quality grade, they should contact an nec sales representative in advance. anti-radioactive design is not implemented in this product. m4 96. 5

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